On 02/14/2014 10:36 AM, Appana Durga Kedareswara Rao wrote:
>>> +/* CAN register bit masks - XCAN___MASK */
>>> +#define XCAN_SRR_CEN_MASK 0x0002 /* CAN enable */
>>> +#define XCAN_SRR_RESET_MASK0x0001 /* Soft Reset the
>> CAN core */
>>> +#define XCAN_MSR_LBACK_MAS
On 02/14/2014 10:13 AM, Michal Simek wrote:
>>> That's not entirely truth. If you look at Microblaze then you will see
>>> that Microblaze can be BE and LE.
>>> There is just missing endian detection which we will add to the next
>>> version.
>>
>> As far as I know the endianess of the kernel is f
On 02/14/2014 10:04 AM, Marc Kleine-Budde wrote:
> On 02/14/2014 09:55 AM, Michal Simek wrote:
>> Hi Marc,
>>
+ int waiting_ech_skb_num;
+ int xcan_echo_skb_max_tx;
+ int xcan_echo_skb_max_rx;
+ struct napi_struct napi;
+ spinlock_t ech_skb_lock;
+ u32 (*read_reg
On 02/14/2014 09:55 AM, Michal Simek wrote:
> Hi Marc,
>
>>> + int waiting_ech_skb_num;
>>> + int xcan_echo_skb_max_tx;
>>> + int xcan_echo_skb_max_rx;
>>> + struct napi_struct napi;
>>> + spinlock_t ech_skb_lock;
>>> + u32 (*read_reg)(const struct xcan_priv *priv, int reg);
>>> + vo
Hi Marc,
>> +int waiting_ech_skb_num;
>> +int xcan_echo_skb_max_tx;
>> +int xcan_echo_skb_max_rx;
>> +struct napi_struct napi;
>> +spinlock_t ech_skb_lock;
>> +u32 (*read_reg)(const struct xcan_priv *priv, int reg);
>> +void (*write_reg)(const struct xcan_priv *priv, in
On 02/12/2014 08:10 AM, Kedareswara rao Appana wrote:
> This patch adds xilinx CAN controller support.
> This driver supports both ZYNQ CANPS IP and
> Soft IP AXI CAN controller.
>
> Signed-off-by: Kedareswara rao Appana
> ---
> This patch is rebased on the 3.14 rc2 kernel.
> Changes for v2:
> -
This patch adds xilinx CAN controller support.
This driver supports both ZYNQ CANPS IP and
Soft IP AXI CAN controller.
Signed-off-by: Kedareswara rao Appana
---
This patch is rebased on the 3.14 rc2 kernel.
Changes for v2:
- Updated with the review comments.
- Removed unnecessary debug prints.
-
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