Re: [PATCH v2] arm64: Add support for new control bits CTR_EL0.DIC and CTR_EL0.IDC

2018-02-21 Thread Shanker Donthineni
Hi Catalin, On 02/21/2018 05:12 AM, Catalin Marinas wrote: > On Mon, Feb 19, 2018 at 08:59:06PM -0600, Shanker Donthineni wrote: >> diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig >> index f55fe5b..4061210 100644 >> --- a/arch/arm64/Kconfig >> +++ b/arch/arm64/Kconfig >> @@ -1095,6 +1095,27 @

Re: [PATCH v2] arm64: Add support for new control bits CTR_EL0.DIC and CTR_EL0.IDC

2018-02-21 Thread Will Deacon
On Wed, Feb 21, 2018 at 07:10:34AM -0600, Shanker Donthineni wrote: > On 02/21/2018 05:12 AM, Catalin Marinas wrote: > > However, my worry is that in an implementation with DIC set, we also > > skip the DSB/ISB sequence in the invalidate_icache_by_line macro. For > > example, in an implementation w

Re: [PATCH v2] arm64: Add support for new control bits CTR_EL0.DIC and CTR_EL0.IDC

2018-02-21 Thread Catalin Marinas
On Mon, Feb 19, 2018 at 08:59:06PM -0600, Shanker Donthineni wrote: > diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig > index f55fe5b..4061210 100644 > --- a/arch/arm64/Kconfig > +++ b/arch/arm64/Kconfig > @@ -1095,6 +1095,27 @@ config ARM64_RAS_EXTN > and access the new registers if t

[PATCH v2] arm64: Add support for new control bits CTR_EL0.DIC and CTR_EL0.IDC

2018-02-19 Thread Shanker Donthineni
The DCache clean & ICache invalidation requirements for instructions to be data coherence are discoverable through new fields in CTR_EL0. The following two control bits DIC and IDC were defined for this purpose. No need to perform point of unification cache maintenance operations from software on s