On 28/11/14 10:38, Liviu Dudau wrote:
> On Fri, Nov 28, 2014 at 03:12:52AM +, Jisheng Zhang wrote:
>> Dear Marc and Liviu,
>>
>> On Thu, 27 Nov 2014 10:39:28 -0800
>> Marc Zyngier wrote:
>>
>>> On 27/11/14 16:21, Liviu Dudau wrote:
The Cortex-A5x TRM states in paragraph "9.2 Generic Timer
On Fri, 28 Nov 2014 02:38:43 -0800
Liviu Dudau wrote:
> On Fri, Nov 28, 2014 at 03:12:52AM +, Jisheng Zhang wrote:
> > Dear Marc and Liviu,
> >
> > On Thu, 27 Nov 2014 10:39:28 -0800
> > Marc Zyngier wrote:
> >
> > > On 27/11/14 16:21, Liviu Dudau wrote:
> > > > The Cortex-A5x TRM states i
On Fri, Nov 28, 2014 at 03:12:52AM +, Jisheng Zhang wrote:
> Dear Marc and Liviu,
>
> On Thu, 27 Nov 2014 10:39:28 -0800
> Marc Zyngier wrote:
>
> > On 27/11/14 16:21, Liviu Dudau wrote:
> > > The Cortex-A5x TRM states in paragraph "9.2 Generic Timer functional
> > > description" that generi
Dear Marc and Liviu,
On Thu, 27 Nov 2014 10:39:28 -0800
Marc Zyngier wrote:
> On 27/11/14 16:21, Liviu Dudau wrote:
> > The Cortex-A5x TRM states in paragraph "9.2 Generic Timer functional
> > description" that generic timers provide a level not edge interrupt
> > output. Fix the device trees to
On 27/11/14 16:21, Liviu Dudau wrote:
> The Cortex-A5x TRM states in paragraph "9.2 Generic Timer functional
> description" that generic timers provide a level not edge interrupt
> output. Fix the device trees to correctly describe this.
>
> While doing this update the CPU mask to match the number
The Cortex-A5x TRM states in paragraph "9.2 Generic Timer functional
description" that generic timers provide a level not edge interrupt
output. Fix the device trees to correctly describe this.
While doing this update the CPU mask to match the number of described
CPUs as well as the DT bindings do
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