On Tue, May 08, 2018 at 11:22:36AM +1000, NeilBrown wrote:
> On Mon, May 07 2018, James Hogan wrote:
>
> > On Mon, May 07, 2018 at 07:40:49AM +1000, NeilBrown wrote:
> >>
> >> Hi James,
> >> this hasn't appear in linux-next yet, or in any branch
> >> of
> >>git://git.kernel.org/pub/scm/linu
On Mon, May 07 2018, James Hogan wrote:
> On Mon, May 07, 2018 at 07:40:49AM +1000, NeilBrown wrote:
>>
>> Hi James,
>> this hasn't appear in linux-next yet, or in any branch
>> of
>>git://git.kernel.org/pub/scm/linux/kernel/git/jhogan/mips.git
>>
>> Should I expect it to?
>
> Sorry Neil,
On Mon, May 07, 2018 at 07:40:49AM +1000, NeilBrown wrote:
>
> Hi James,
> this hasn't appear in linux-next yet, or in any branch
> of
>git://git.kernel.org/pub/scm/linux/kernel/git/jhogan/mips.git
>
> Should I expect it to?
Sorry Neil, I haven't applied it yet. I'm planning to get a few
Hi James,
this hasn't appear in linux-next yet, or in any branch
of
git://git.kernel.org/pub/scm/linux/kernel/git/jhogan/mips.git
Should I expect it to?
Thanks,
NeilBrown
On Fri, Apr 27 2018, NeilBrown wrote:
> When DMA will be performed to a MIPS32 1004K CPS, the
> L1-cache for the rang
When DMA will be performed to a MIPS32 1004K CPS, the
L1-cache for the range needs to be flushed and invalidated
first.
The code currently takes one of two approaches.
1/ If the range is less than the size of the dcache, then
HIT type requests flush/invalidate cache lines for the
particular
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