On Tue, 05 May 2015, Eric Anholt wrote:
> There exists a tiny MMU, configurable only by the VC (running the
> closed firmware), which maps from the ARM's physical addresses to bus
> addresses. These bus addresses determine the caching behavior in the
> VC's L1/L2 (note: separate from the ARM's L1
There exists a tiny MMU, configurable only by the VC (running the
closed firmware), which maps from the ARM's physical addresses to bus
addresses. These bus addresses determine the caching behavior in the
VC's L1/L2 (note: separate from the ARM's L1/L2) according to the top
2 bits. The bits in th
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