Re: [PATCH v1 2/2] riscv: Clean up module relocations

On Thu, 30 Jul 2020 at 20:53, Luke Nelson wrote: > > Thanks for the patch! > > > Also RISC-V has a number of instruction pairs to > > generate 32bit immediates or jump/call offsets. Eg.: > > > > lui rd, hi20 > > addi rd, rd, lo12 > > On RV64, both hi20 from lui and lo12 from addi are sign-exten

Re: [PATCH v1 2/2] riscv: Clean up module relocations

Thanks for the patch! > Also RISC-V has a number of instruction pairs to > generate 32bit immediates or jump/call offsets. Eg.: > > lui rd, hi20 > addi rd, rd, lo12 On RV64, both hi20 from lui and lo12 from addi are sign-extended to 64 bits. This means that there are some 32-bit signed offsets

[PATCH v1 2/2] riscv: Clean up module relocations

Factor out generation of different types of immediates. Also RISC-V has a number of instruction pairs to generate 32bit immediates or jump/call offsets. Eg.: lui rd, hi20 addi rd, rd, lo12 ..where hi20 is the upper 20bits to load into register rd and lo12 is the lower 12bits. However lo12 is