Quoting Kim, Cheol Yong (2019-09-09 07:16:29)
>
> I've discussed internally the amount of efforts to create a reusable
> regmap clock driver which might be reused by other companies too.
>
> It seems it requires significant efforts for implementation/tests. As we
> don't plan to support our old
On 9/6/2019 4:47 AM, Martin Blumenstingl wrote:
Hi Rahul,
On Wed, Sep 4, 2019 at 10:04 AM Tanwar, Rahul
wrote:
Hi Martin,
On 4/9/2019 2:53 AM, Martin Blumenstingl wrote:
My understanding is that if we do not use syscon, then there is no
point in using regmap because this driver uses simpl
Hi Rahul,
On Wed, Sep 4, 2019 at 10:04 AM Tanwar, Rahul
wrote:
>
>
> Hi Martin,
>
> On 4/9/2019 2:53 AM, Martin Blumenstingl wrote:
> >> My understanding is that if we do not use syscon, then there is no
> >> point in using regmap because this driver uses simple 32 bit register
> >> access. Can d
Hi Martin,
On 4/9/2019 2:53 AM, Martin Blumenstingl wrote:
My understanding is that if we do not use syscon, then there is no
point in using regmap because this driver uses simple 32 bit register
access. Can directly read/write registers using readl() & writel().
Would you agree ?
if there w
Quoting Martin Blumenstingl (2019-09-02 15:20:15)
> +struct intel_clk_gate {
> + struct clk_hw hw;
> + struct device *dev;
> + struct regmap *map;
> + unsigned int reg;
> + u8 shift;
> + unsigned long flags;
> +};
> I know at least two existing regmap clock imple
Hi Rahul,
On Tue, Sep 3, 2019 at 11:54 AM Tanwar, Rahul
wrote:
>
>
> Hi Martin,
>
> On 3/9/2019 6:20 AM, Martin Blumenstingl wrote:
> > Hello,
> >
> > I only noticed this patchset today and I don't have much time left.
> > Here's my initial impressions without going through the code in detail.
>
Hi Martin,
On 3/9/2019 6:20 AM, Martin Blumenstingl wrote:
Hello,
I only noticed this patchset today and I don't have much time left.
Here's my initial impressions without going through the code in detail.
I'll continue my review in the next days (as time permits).
As with all other Intel LG
Hello,
I only noticed this patchset today and I don't have much time left.
Here's my initial impressions without going through the code in detail.
I'll continue my review in the next days (as time permits).
As with all other Intel LGM patches: I don't have access to the
datasheets, so it's possib
On Mon, Sep 02, 2019 at 03:20:30PM +0300, Andy Shevchenko wrote:
> On Mon, Sep 02, 2019 at 03:43:13PM +0800, Tanwar, Rahul wrote:
> > On 28/8/2019 11:09 PM, Andy Shevchenko wrote:
> > > On Wed, Aug 28, 2019 at 03:00:17PM +0800, Rahul Tanwar wrote:
> > > Does val == 0 follows the table, i.e. makes
On Mon, Sep 02, 2019 at 03:43:13PM +0800, Tanwar, Rahul wrote:
> On 28/8/2019 11:09 PM, Andy Shevchenko wrote:
> > On Wed, Aug 28, 2019 at 03:00:17PM +0800, Rahul Tanwar wrote:
> > > drivers/clk/intel/Kconfig | 13 +
> > > drivers/clk/intel/Makefile | 4 +
> > Any plans what to do
Hi Andy,
Thanks for your review comments.
On 28/8/2019 11:09 PM, Andy Shevchenko wrote:
On Wed, Aug 28, 2019 at 03:00:17PM +0800, Rahul Tanwar wrote:
From: rtanwar
Clock Generation Unit(CGU) is a new clock controller IP of a forthcoming
Intel network processor SoC. It provides programming
On Wed, Aug 28, 2019 at 03:00:17PM +0800, Rahul Tanwar wrote:
> From: rtanwar
>
> Clock Generation Unit(CGU) is a new clock controller IP of a forthcoming
> Intel network processor SoC. It provides programming interfaces to control
> & configure all CPU & peripheral clocks. Add common clock frame
From: rtanwar
Clock Generation Unit(CGU) is a new clock controller IP of a forthcoming
Intel network processor SoC. It provides programming interfaces to control
& configure all CPU & peripheral clocks. Add common clock framework based
clock controller driver for CGU.
Signed-off-by: Rahul Tanwar
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