Re: [PATCH v1 0/4] KVM: MMU: 5 level EPT/shadow support

2017-08-14 Thread Paolo Bonzini
On 12/08/2017 15:35, Yu Zhang wrote: > Intel's existing processors limit the maximum linear address width to > 48 bits, and the maximum physical address width to 46 bits. And the > upcoming processors will extend maximum linear address width to 57 bits > and maximum physical address width can go up

[PATCH v1 0/4] KVM: MMU: 5 level EPT/shadow support

2017-08-12 Thread Yu Zhang
Intel's existing processors limit the maximum linear address width to 48 bits, and the maximum physical address width to 46 bits. And the upcoming processors will extend maximum linear address width to 57 bits and maximum physical address width can go upto 52 bits in practical. With linear address