Hello folks,
My comments are below.
On Wed, Jan 06, 2021 at 01:44:28PM +0200, Andy Shevchenko wrote:
> On Wednesday, January 6, 2021, Bartosz Golaszewski <
> bgolaszew...@baylibre.com> wrote:
>
> > On Mon, Dec 7, 2020 at 2:10 PM luojiaxing wrote:
> > >
> > >
> > > On 2020/12/7 2:50, Marc Zyngier
On Mon, Dec 7, 2020 at 2:10 PM luojiaxing wrote:
>
>
> On 2020/12/7 2:50, Marc Zyngier wrote:
> > On 2020-12-06 15:02, Linus Walleij wrote:
> >> On Sat, Dec 5, 2020 at 11:15 PM Serge Semin
> >> wrote:
> >>
> >>> Hmm, that sounds like a problem, but the explanation is a bit unclear
> >>> to me. AF
On 2020/12/7 2:50, Marc Zyngier wrote:
On 2020-12-06 15:02, Linus Walleij wrote:
On Sat, Dec 5, 2020 at 11:15 PM Serge Semin
wrote:
Hmm, that sounds like a problem, but the explanation is a bit unclear
to me. AFAICS you are saying that the only callbacks which are
called during the IRQ req
On 2020/12/6 23:02, Linus Walleij wrote:
On Sat, Dec 5, 2020 at 11:15 PM Serge Semin wrote:
Hmm, that sounds like a problem, but the explanation is a bit unclear
to me. AFAICS you are saying that the only callbacks which are
called during the IRQ request/release are the irq_enable(), right?
On 2020/12/6 6:15, Serge Semin wrote:
On Tue, Dec 01, 2020 at 04:59:21PM +0800, luojiaxing wrote:
On 2020/11/30 19:22, Andy Shevchenko wrote:
On Mon, Nov 30, 2020 at 05:36:19PM +0800, Luo Jiaxing wrote:
The mask and unmask registers are not configured in dwapb_irq_enable() and
dwapb_irq_disa
On 2020-12-06 15:02, Linus Walleij wrote:
On Sat, Dec 5, 2020 at 11:15 PM Serge Semin
wrote:
Hmm, that sounds like a problem, but the explanation is a bit unclear
to me. AFAICS you are saying that the only callbacks which are
called during the IRQ request/release are the irq_enable(), right?
On Sat, Dec 5, 2020 at 11:15 PM Serge Semin wrote:
> Hmm, that sounds like a problem, but the explanation is a bit unclear
> to me. AFAICS you are saying that the only callbacks which are
> called during the IRQ request/release are the irq_enable(), right? If
> so then the only reason why we have
On Tue, Dec 01, 2020 at 04:59:21PM +0800, luojiaxing wrote:
>
> On 2020/11/30 19:22, Andy Shevchenko wrote:
> > On Mon, Nov 30, 2020 at 05:36:19PM +0800, Luo Jiaxing wrote:
> > > The mask and unmask registers are not configured in dwapb_irq_enable() and
> > > dwapb_irq_disable(). In the following
Sorry for top posting but I need the help of the irqchip maintainer
Marc Z to hash this out.
The mask/unmask/disable/enable semantics is something that
you need to work with every day to understand right.
Yours,
Linus Walleij
On Mon, Nov 30, 2020 at 10:36 AM Luo Jiaxing wrote:
>
> The mask and
On 2020/11/30 19:22, Andy Shevchenko wrote:
On Mon, Nov 30, 2020 at 05:36:19PM +0800, Luo Jiaxing wrote:
The mask and unmask registers are not configured in dwapb_irq_enable() and
dwapb_irq_disable(). In the following situations, the IRQ will be masked by
default after the IRQ is enabled:
mas
On Mon, Nov 30, 2020 at 05:36:19PM +0800, Luo Jiaxing wrote:
> The mask and unmask registers are not configured in dwapb_irq_enable() and
> dwapb_irq_disable(). In the following situations, the IRQ will be masked by
> default after the IRQ is enabled:
>
> mask IRQ -> disable IRQ -> enable IRQ
>
>
The mask and unmask registers are not configured in dwapb_irq_enable() and
dwapb_irq_disable(). In the following situations, the IRQ will be masked by
default after the IRQ is enabled:
mask IRQ -> disable IRQ -> enable IRQ
In this case, the IRQ status of GPIO controller is inconsistent with it's
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