Hi Andrew,
Andrew Lunn writes:
> It does result in more patches, more to review, but it is much easier
> to review, because it should be obviously correct. The overall lines
> of code at the end is the same. So overall there is no harm is having
> lots of small patches.
Your concerns are dully
> > I really wished you had moved the code, unmodified, into
> > global1_atu.c. Then made lots of easy to review small changes. I
> > cannot just look at this patch and know it is correct. What i need to
> > compare against is not in this patch. So it is a lot harder to review.
>
> I've addressed
Hi Andrew,
Andrew Lunn writes:
> On Thu, Mar 09, 2017 at 06:33:14PM -0500, Vivien Didelot wrote:
>> All Marvell switch chips have an ATU accessed using the same Global (1)
>> register layout. Only the handling of the FID differs as more bits were
>> necessary to support more and more databases.
On Thu, Mar 09, 2017 at 06:33:14PM -0500, Vivien Didelot wrote:
> All Marvell switch chips have an ATU accessed using the same Global (1)
> register layout. Only the handling of the FID differs as more bits were
> necessary to support more and more databases.
>
> Add and use a fresh documented imp
All Marvell switch chips have an ATU accessed using the same Global (1)
register layout. Only the handling of the FID differs as more bits were
necessary to support more and more databases.
Add and use a fresh documented implementation of the ATU Load/Purge.
Signed-off-by: Vivien Didelot
---
dr
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