On 01/08/2013 03:57 AM, Laxman Dewangan wrote:
> NVIDIA's Tegra has multiple UART controller which supports:
> - APB DMA based controller fifo read/write.
> - End Of Data interrupt in incoming data to know whether end
> of frame achieve or not.
> - HW controlled RTS and CTS flow control to reduce
NVIDIA's Tegra has multiple UART controller which supports:
- APB DMA based controller fifo read/write.
- End Of Data interrupt in incoming data to know whether end
of frame achieve or not.
- HW controlled RTS and CTS flow control to reduce SW overhead.
Add serial driver to use all above feature
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