On 09/24/13 11:06, Andrew Bresticker wrote:
> +static int __init exynos_audss_clk_init(void)
> +{
> + return platform_driver_register(&exynos_audss_clk_driver);
> +}
> +core_initcall(exynos_audss_clk_init);
> +
> +static void __init exynos_audss_clk_exit(void)
__exit?
> +{
> + platform_dr
>> +static int exynos_audss_clk_remove(struct platform_device *pdev)
>> +{
>> + int i;
>> +
>> + of_clk_del_provider(pdev->dev.of_node);
>> +
>> + for (i = 0; i< EXYNOS_AUDSS_MAX_CLKS; i++) {
>> + if (!IS_ERR_OR_NULL(clk_table[i]))
>> + clk_unr
On 09/24/2013 08:06 PM, Andrew Bresticker wrote:
+static int exynos_audss_clk_probe(struct platform_device *pdev)
{
[...]
clk_table[EXYNOS_MOUT_AUDSS] = clk_register_mux(NULL, "mout_audss",
mout_audss_p, ARRAY_SIZE(mout_audss_p),
@@ -123,13 +124,83 @@ s
Hi Andrew,
On Tuesday 24 of September 2013 11:06:51 Andrew Bresticker wrote:
> The Exynos AudioSS clock controller will later be modified to allow
> input clocks to be specified via device-tree in order to support
> multiple Exynos SoCs. This will introduce a dependency on the core
> SoC clock co
The Exynos AudioSS clock controller will later be modified to allow
input clocks to be specified via device-tree in order to support
multiple Exynos SoCs. This will introduce a dependency on the core
SoC clock controller being initialized first so that the AudioSS driver
can look up its input cloc
5 matches
Mail list logo