Re: [PATCH RFC 0/4] 5-level EPT

2017-03-10 Thread Yu Zhang
On 3/9/2017 10:16 PM, Paolo Bonzini wrote: On 17/01/2017 03:18, Li, Liang Z wrote: On 29/12/2016 10:25, Liang Li wrote: x86-64 is currently limited physical address width to 46 bits, which can support 64 TiB of memory. Some vendors require to support more for some use case. Intel plans to ex

Re: [PATCH RFC 0/4] 5-level EPT

2017-03-09 Thread Paolo Bonzini
On 17/01/2017 03:18, Li, Liang Z wrote: >> On 29/12/2016 10:25, Liang Li wrote: >>> x86-64 is currently limited physical address width to 46 bits, which >>> can support 64 TiB of memory. Some vendors require to support more for >>> some use case. Intel plans to extend the physical address width t

RE: [PATCH RFC 0/4] 5-level EPT

2017-01-16 Thread Li, Liang Z
> On 29/12/2016 10:25, Liang Li wrote: > > x86-64 is currently limited physical address width to 46 bits, which > > can support 64 TiB of memory. Some vendors require to support more for > > some use case. Intel plans to extend the physical address width to > > 52 bits in some of the future product

Re: [PATCH RFC 0/4] 5-level EPT

2017-01-05 Thread Kirill A. Shutemov
On Thu, Dec 29, 2016 at 05:25:59PM +0800, Liang Li wrote: > x86-64 is currently limited physical address width to 46 bits, which > can support 64 TiB of memory. Some vendors require to support more for > some use case. Intel plans to extend the physical address width to > 52 bits in some of the fut

Re: [PATCH RFC 0/4] 5-level EPT

2017-01-02 Thread Paolo Bonzini
On 29/12/2016 10:25, Liang Li wrote: > x86-64 is currently limited physical address width to 46 bits, which > can support 64 TiB of memory. Some vendors require to support more for > some use case. Intel plans to extend the physical address width to > 52 bits in some of the future products. > >

RE: [PATCH RFC 0/4] 5-level EPT

2016-12-29 Thread Li, Liang Z
> Subject: Re: [PATCH RFC 0/4] 5-level EPT > > On Thu, 29 Dec 2016 17:25:59 +0800, Liang Li said: > > x86-64 is currently limited physical address width to 46 bits, which > > can support 64 TiB of memory. Some vendors require to support more for > > some use case

Re: [PATCH RFC 0/4] 5-level EPT

2016-12-29 Thread Valdis . Kletnieks
On Thu, 29 Dec 2016 17:25:59 +0800, Liang Li said: > x86-64 is currently limited physical address width to 46 bits, which > can support 64 TiB of memory. Some vendors require to support more for > some use case. Intel plans to extend the physical address width to > 52 bits in some of the future pro

[PATCH RFC 0/4] 5-level EPT

2016-12-29 Thread Liang Li
x86-64 is currently limited physical address width to 46 bits, which can support 64 TiB of memory. Some vendors require to support more for some use case. Intel plans to extend the physical address width to 52 bits in some of the future products. The current EPT implementation only supports 4 le