Re: [PATCH RESEND v2 1/1] ARM Feroceon: fix kexec by setting outer_cache.inv_all

2013-04-10 Thread Elijah Ragozin
On 10.04.2013 19:48, Jason Cooper wrote: On Mon, Apr 08, 2013 at 10:34:07PM +0300, Elijah Ragozin wrote: On Feroceon the L2 cache becomes non-coherent with the CPU when the L1 caches are disabled. Thus the L2 needs to be invalidated after both L1 caches are disabled. On kexec before the startin

Re: [PATCH RESEND v2 1/1] ARM Feroceon: fix kexec by setting outer_cache.inv_all

2013-04-10 Thread Jason Cooper
On Mon, Apr 08, 2013 at 10:34:07PM +0300, Elijah Ragozin wrote: > On Feroceon the L2 cache becomes non-coherent with the CPU > when the L1 caches are disabled. Thus the L2 needs to be invalidated > after both L1 caches are disabled. > > On kexec before the starting the code for relocation the kern

[PATCH RESEND v2 1/1] ARM Feroceon: fix kexec by setting outer_cache.inv_all

2013-04-08 Thread Elijah Ragozin
On Feroceon the L2 cache becomes non-coherent with the CPU when the L1 caches are disabled. Thus the L2 needs to be invalidated after both L1 caches are disabled. On kexec before the starting the code for relocation the kernel, the L1 caches are disabled in cpu_froc_fin (cpu_v7_proc_fin for Feroc

Fwd: [PATCH RESEND v2 1/1] ARM Feroceon: fix kexec by setting outer_cache.inv_all

2013-04-08 Thread Elijah Ragozin
On Feroceon the L2 cache becomes non-coherent with the CPU when the L1 caches are disabled. Thus the L2 needs to be invalidated after both L1 caches are disabled. On kexec before the starting the code for relocation the kernel, the L1 caches are disabled in cpu_froc_fin (cpu_v7_proc_fin for Feroc