On Thu, Aug 02, 2018 at 12:04:04PM +0200, Thomas Gleixner wrote:
>
> On Thu, 26 Jul 2018, Christoph Hellwig wrote:
>
> > This patch adds a driver for the Platform Level Interrupt Controller (PLIC)
>
> See Documentation/process/submitting-patches.rst and search for 'This patch'
Fixed.
> > +stat
On Thu, 26 Jul 2018, Christoph Hellwig wrote:
> This patch adds a driver for the Platform Level Interrupt Controller (PLIC)
See Documentation/process/submitting-patches.rst and search for 'This patch'
> +static inline void __iomem *plic_hart_offset(int ctxid)
> +{
> + return plic_regs + CO
On Wed, Aug 01, 2018 at 06:09:42PM -0700, Atish Patra wrote:
> On 8/1/18 5:12 AM, Christoph Hellwig wrote:
>> On Tue, Jul 31, 2018 at 05:38:01PM -0700, Atish Patra wrote:
>>> crash details are at
>>> https://paste.debian.net/1036078/
>>
>> Is this running without kallsyms? It seems to lack useful
On Wed, Aug 01, 2018 at 06:02:52PM -0700, Atish Patra wrote:
> But can we keep the new kconfig option "SIFIVE_PLIC" enabled in
> driver/irqchip/Kconfig or arch/riscv/Kconfig for now to avoid breakage
> without linux_defconfig update.
I'll update arch/riscv/configs/defconfig for the next repost.
On 8/1/18 5:12 AM, Christoph Hellwig wrote:
On Tue, Jul 31, 2018 at 05:38:01PM -0700, Atish Patra wrote:
crash details are at
https://paste.debian.net/1036078/
Is this running without kallsyms? It seems to lack useful symbols
and a backtrace unfortunately.
Yes. I checked the config. All KAL
On 8/1/18 7:14 AM, Christoph Hellwig wrote:
I've pushed out an update to the riscv-irq-simple.2 branch to better
handle with sparse contexid maps, please retry with that.
I see you have changed the driver file name from irq-riscv-plic to
irq-riscv-sifive along with default Y for SIFIVE_PLIC.
I've pushed out an update to the riscv-irq-simple.2 branch to better
handle with sparse contexid maps, please retry with that.
On Tue, Jul 31, 2018 at 05:38:01PM -0700, Atish Patra wrote:
> crash details are at
> https://paste.debian.net/1036078/
Is this running without kallsyms? It seems to lack useful symbols
and a backtrace unfortunately.
On Tue, Jul 31, 2018 at 05:38:01PM -0700, Atish Patra wrote:
> Some typos in the above repo in the PLIC driver patch. The following
> changes are required. Inline patch below
Thanks, I'll fold this in.
> With the above changes, I am able to boot quite far. But it still crashes
> which may be a
On 7/31/18 9:52 AM, Christoph Hellwig wrote:
On Mon, Jul 30, 2018 at 08:21:33PM -0700, Atish Patra wrote:
I found the issue. As per PLIC documentation, a hart context is a given
privilege mode on a given hart. Thus, cpu context ID & cpu numbers are not
same. Here is the PLIC register Maps in U54
On Mon, Jul 30, 2018 at 08:21:33PM -0700, Atish Patra wrote:
> I found the issue. As per PLIC documentation, a hart context is a given
> privilege mode on a given hart. Thus, cpu context ID & cpu numbers are not
> same. Here is the PLIC register Maps in U54 core:
>
> Ref: https://static.dev.sifiv
On Fri, Jul 27, 2018 at 05:04:52PM -0700, Atish Patra wrote:
>> +#define MAX_DEVICES 1024
>> +#define MAX_CONTEXTS15872
>> +
>
> Is there any way we can preserve some of the comments in the original patch
> about memory-mapped control registers or at least a
On 7/27/18 5:04 PM, Atish Patra wrote:
On 7/26/18 7:38 AM, Christoph Hellwig wrote:
This patch adds a driver for the Platform Level Interrupt Controller (PLIC)
specified as part of the RISC-V supervisor level ISA manual, in the memory
layout implemented by SiFive and qemu.
The PLIC connects glo
On Sat 28 Jul, 2018, 5:34 AM Atish Patra, wrote:
>
> On 7/26/18 7:38 AM, Christoph Hellwig wrote:
> > This patch adds a driver for the Platform Level Interrupt Controller (PLIC)
> > specified as part of the RISC-V supervisor level ISA manual, in the memory
> > layout implemented by SiFive and qemu
On 7/26/18 7:38 AM, Christoph Hellwig wrote:
This patch adds a driver for the Platform Level Interrupt Controller (PLIC)
specified as part of the RISC-V supervisor level ISA manual, in the memory
layout implemented by SiFive and qemu.
The PLIC connects global interrupt sources to the local inter
This patch adds a driver for the Platform Level Interrupt Controller (PLIC)
specified as part of the RISC-V supervisor level ISA manual, in the memory
layout implemented by SiFive and qemu.
The PLIC connects global interrupt sources to the local interrupt controller
on each hart.
This driver is b
16 matches
Mail list logo
