Hi Max,
We could probably still use NMI with a separate stack. However, for
exception handling while in NMI, we might have to implement something
similar to x86_64 (https://lwn.net/Articles/484932/).
Cheers!
-Chris
On Mon, Jul 6, 2015 at 7:22 AM, Max Filippov wrote:
> On Mon, Jul 6, 2015 at 5:0
On Mon, Jul 6, 2015 at 5:05 PM, Peter Zijlstra wrote:
> On Mon, Jul 06, 2015 at 04:56:09PM +0300, Max Filippov wrote:
>> On Mon, Jul 6, 2015 at 4:47 PM, Peter Zijlstra wrote:
>> > On Mon, Jul 06, 2015 at 04:32:48PM +0300, Max Filippov wrote:
>> >> +static int __init xtensa_pmu_init(void)
>> >> +{
On Mon, Jul 06, 2015 at 04:56:09PM +0300, Max Filippov wrote:
> On Mon, Jul 6, 2015 at 4:47 PM, Peter Zijlstra wrote:
> > On Mon, Jul 06, 2015 at 04:32:48PM +0300, Max Filippov wrote:
> >> +static int __init xtensa_pmu_init(void)
> >> +{
> >> + int ret;
> >> + int irq = irq_create_mapping(
On Mon, Jul 6, 2015 at 4:47 PM, Peter Zijlstra wrote:
> On Mon, Jul 06, 2015 at 04:32:48PM +0300, Max Filippov wrote:
>> +static int __init xtensa_pmu_init(void)
>> +{
>> + int ret;
>> + int irq = irq_create_mapping(NULL, XCHAL_PROFILING_INTERRUPT);
>
> Does this platform have interrupt pr
On Mon, Jul 6, 2015 at 4:41 PM, Peter Zijlstra wrote:
> Since this PMU implements TYPE_HARDWARE/TYPE_HW_CACHE/TYPE_RAW,
> returning -ENOENT for those is wrong.
>
> If the configuration is invalid, return -EINVAL.
Ok.
--
Thanks.
-- Max
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On Mon, Jul 06, 2015 at 04:32:48PM +0300, Max Filippov wrote:
> +static int __init xtensa_pmu_init(void)
> +{
> + int ret;
> + int irq = irq_create_mapping(NULL, XCHAL_PROFILING_INTERRUPT);
Does this platform have interrupt priorities which you can partially
mask in order to create NMI lik
On Mon, Jul 06, 2015 at 04:32:48PM +0300, Max Filippov wrote:
> +static int xtensa_pmu_event_init(struct perf_event *event)
> +{
> + int ret;
> +
> + switch (event->attr.type) {
> + case PERF_TYPE_HARDWARE:
> + if (event->attr.config >= ARRAY_SIZE(xtensa_hw_ctl) ||
> +
Xtensa Performance Monitor Module has up to 8 32 bit wide performance
counters. Each counter may be enabled independently and can count any
single type of hardware performance events. Event counting may be enabled
and disabled globally (per PMM).
Each counter has status register with bits indicatin
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