On Thu, Jun 5, 2014 at 4:21 PM, Peter Zijlstra wrote:
> On Thu, Jun 05, 2014 at 04:15:17PM +0200, Stephane Eranian wrote:
>> On Thu, Jun 5, 2014 at 4:04 PM, Peter Zijlstra wrote:
>> > On Wed, Jun 04, 2014 at 11:34:14PM +0200, Stephane Eranian wrote:
>> >> +
>> >> + /*
>> >> + * Modify st
On Thu, Jun 05, 2014 at 04:26:38PM +0200, Stephane Eranian wrote:
> On Thu, Jun 5, 2014 at 4:21 PM, Peter Zijlstra wrote:
> > We could limit each cpu to num_counters/2 exclusive slots. That'll still
> > be painful with some constrained events I imagine, but in general that
> > should 'work' I sup
On Thu, Jun 5, 2014 at 4:21 PM, Peter Zijlstra wrote:
> On Thu, Jun 05, 2014 at 04:15:17PM +0200, Stephane Eranian wrote:
>> On Thu, Jun 5, 2014 at 4:04 PM, Peter Zijlstra wrote:
>> > On Wed, Jun 04, 2014 at 11:34:14PM +0200, Stephane Eranian wrote:
>> >> +
>> >> + /*
>> >> + * Modify st
On Thu, Jun 5, 2014 at 5:14 PM, Peter Zijlstra wrote:
> On Thu, Jun 05, 2014 at 04:11:50PM +0200, Peter Zijlstra wrote:
>> > > x86_schedule_event()
>> > > ->start_scheduling()
>> > > spin_lock()
>> > > ->get_event_constraints()
>> > > intel_get_excl_constraints()
>> > > kmalloc(.
On Thu, Jun 05, 2014 at 04:15:17PM +0200, Stephane Eranian wrote:
> On Thu, Jun 5, 2014 at 4:04 PM, Peter Zijlstra wrote:
> > On Wed, Jun 04, 2014 at 11:34:14PM +0200, Stephane Eranian wrote:
> >> +
> >> + /*
> >> + * Modify static constraint with current dynamic
> >> + * state of th
On Thu, Jun 5, 2014 at 4:04 PM, Peter Zijlstra wrote:
> On Wed, Jun 04, 2014 at 11:34:14PM +0200, Stephane Eranian wrote:
>> +
>> + /*
>> + * Modify static constraint with current dynamic
>> + * state of thread
>> + *
>> + * EXCLUSIVE: sibling counter measuring exclusive ev
On Thu, Jun 05, 2014 at 04:11:50PM +0200, Peter Zijlstra wrote:
> > > x86_schedule_event()
> > > ->start_scheduling()
> > > spin_lock()
> > > ->get_event_constraints()
> > > intel_get_excl_constraints()
> > > kmalloc(.gfp=GFP_KERNEL)
> > >
> > > How can that ever work?
>
> > Are
On Thu, Jun 05, 2014 at 05:01:25PM +0300, Maria Dimakopoulou wrote:
> On Thu, Jun 5, 2014 at 4:48 PM, Peter Zijlstra wrote:
> > On Wed, Jun 04, 2014 at 11:34:14PM +0200, Stephane Eranian wrote:
> >
> >> +static struct event_constraint *
> >> +intel_get_excl_constraints(struct cpu_hw_events *cpuc,
On Thu, Jun 05, 2014 at 05:01:25PM +0300, Maria Dimakopoulou wrote:
> Are you saying it is illegal to call kmalloc() from
> this context?
>
> kmalloc is needed because we need to allocate
> a new constraint struct since the static constraint
> cannot be modified.
>
> Worst case we can statically
On Wed, Jun 04, 2014 at 11:34:14PM +0200, Stephane Eranian wrote:
> +
> + /*
> + * Modify static constraint with current dynamic
> + * state of thread
> + *
> + * EXCLUSIVE: sibling counter measuring exclusive event
> + * SHARED : sibling counter measuring non-exclusi
Are you saying it is illegal to call kmalloc() from
this context?
kmalloc is needed because we need to allocate
a new constraint struct since the static constraint
cannot be modified.
Worst case we can statically allocate a second
constraint struct in the event struct.
On Thu, Jun 5, 2014 at 4:4
On Wed, Jun 04, 2014 at 11:34:14PM +0200, Stephane Eranian wrote:
> +static struct event_constraint *
> +intel_get_excl_constraints(struct cpu_hw_events *cpuc, struct perf_event
> *event,
> +struct event_constraint *c)
> +{
> + if (!(c->flags & PERF_X86_EVENT_DYNAMIC)
On Wed, Jun 04, 2014 at 11:34:14PM +0200, Stephane Eranian wrote:
> +static void intel_commit_scheduling(struct cpu_hw_events *cpuc,
> + struct perf_event *event, int cntr)
> +{
> + struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs;
> + struct event_cons
On Wed, Jun 04, 2014 at 11:34:14PM +0200, Stephane Eranian wrote:
> static void
> +intel_start_scheduling(struct cpu_hw_events *cpuc)
> +{
> + /*
> + * lock shared state until we are done scheduling
> + * in stop_event_scheduling()
> + * makes scheduling appear as a transaction
From: Maria Dimakopoulou
This patch implements a software workaround for a HW erratum
on Intel SandyBridge, IvyBridge and Haswell processors
with Hyperthreading enabled. The errata are documented for
each processor in their respective specification update
documents:
- SandyBridge: BJ122
- IvyBr
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