On Tue, Jun 10, 2014 at 01:53:45PM +0200, Stephane Eranian wrote:
> On Thu, Jun 5, 2014 at 10:29 AM, Peter Zijlstra wrote:
> > On Wed, Jun 04, 2014 at 11:34:13PM +0200, Stephane Eranian wrote:
> >> @@ -2020,12 +2050,29 @@ static void intel_pmu_cpu_starting(int cpu)
> >>
> >> if (x86_pmu.lbr_
On Thu, Jun 5, 2014 at 10:29 AM, Peter Zijlstra wrote:
> On Wed, Jun 04, 2014 at 11:34:13PM +0200, Stephane Eranian wrote:
>> @@ -2020,12 +2050,29 @@ static void intel_pmu_cpu_starting(int cpu)
>>
>> if (x86_pmu.lbr_sel_map)
>> cpuc->lbr_sel = &cpuc->shared_regs->regs[EXTRA_REG
On Thu, Jun 5, 2014 at 11:33 PM, Andi Kleen wrote:
>> This hard assumes theres only ever 2 threads, which is true and I
>> suppose more in arch/x86 will come apart the moment Intel makes a chip
>> with more, still, do we have topology_thread_id() or so to cure this?
>
>
> Xeon Phi already has 4 th
> This hard assumes theres only ever 2 threads, which is true and I
> suppose more in arch/x86 will come apart the moment Intel makes a chip
> with more, still, do we have topology_thread_id() or so to cure this?
Xeon Phi already has 4 threads today.
-Andi
--
a...@linux.intel.com -- Speaking f
This is to indicate that the PMU needs to setup the
shared state struct which is called excl_cntrs.
That struct is allocated for all CPUs at first, and
then half of them are destroyed and their CPUs
made to point to their siblings struct.
So yes. EXCL is really related to HT.
It could be called HT
On Thu, Jun 5, 2014 at 9:47 AM, Peter Zijlstra wrote:
> On Wed, Jun 04, 2014 at 11:34:13PM +0200, Stephane Eranian wrote:
>> From: Maria Dimakopoulou
>>
>> This patch adds a new shared_regs style structure to the
>> per-cpu x86 state (cpuc). It is used to coordinate access
>> between counters whi
On Wed, Jun 04, 2014 at 11:34:13PM +0200, Stephane Eranian wrote:
> @@ -2020,12 +2050,29 @@ static void intel_pmu_cpu_starting(int cpu)
>
> if (x86_pmu.lbr_sel_map)
> cpuc->lbr_sel = &cpuc->shared_regs->regs[EXTRA_REG_LBR];
> +
> + if (x86_pmu.flags & PMU_FL_EXCL_CNTRS) {
On Wed, Jun 04, 2014 at 11:34:13PM +0200, Stephane Eranian wrote:
> @@ -499,6 +530,7 @@ do {
> \
> */
> #define PMU_FL_NO_HT_SHARING 0x1 /* no hyper-threading resource sharing */
> #define PMU_FL_HAS_RSP_1 0x2 /* has 2 eq
On Wed, Jun 04, 2014 at 11:34:13PM +0200, Stephane Eranian wrote:
> From: Maria Dimakopoulou
>
> This patch adds a new shared_regs style structure to the
> per-cpu x86 state (cpuc). It is used to coordinate access
> between counters which must be used with exclusion across
> HyperThreads on Intel
From: Maria Dimakopoulou
This patch adds a new shared_regs style structure to the
per-cpu x86 state (cpuc). It is used to coordinate access
between counters which must be used with exclusion across
HyperThreads on Intel processors. This new struct is not
needed on each PMU, thus is is allocated o
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