Re: [PATCH 2] PNP: Work around BIOS defects in Intel MCH area reporting

2014-04-24 Thread Stephane Eranian
On Thu, Apr 24, 2014 at 9:20 AM, Ingo Molnar wrote: > > * Stephane Eranian wrote: > >> On Tue, Apr 22, 2014 at 12:17 AM, Bjorn Helgaas wrote: >> > Work around BIOSes that don't report the entire Intel MCH area. >> > >> > MCHBAR is not an architected PCI BAR, so MCH space is usually reported as a

Re: [PATCH 2] PNP: Work around BIOS defects in Intel MCH area reporting

2014-04-24 Thread Ingo Molnar
* Stephane Eranian wrote: > On Tue, Apr 22, 2014 at 12:17 AM, Bjorn Helgaas wrote: > > Work around BIOSes that don't report the entire Intel MCH area. > > > > MCHBAR is not an architected PCI BAR, so MCH space is usually reported as a > > PNP0C02 resource. The MCH space was once 16KB, but is 3

Re: [PATCH 2] PNP: Work around BIOS defects in Intel MCH area reporting

2014-04-23 Thread Stephane Eranian
On Tue, Apr 22, 2014 at 12:17 AM, Bjorn Helgaas wrote: > Work around BIOSes that don't report the entire Intel MCH area. > > MCHBAR is not an architected PCI BAR, so MCH space is usually reported as a > PNP0C02 resource. The MCH space was once 16KB, but is 32KB in newer parts. > Some BIOSes still

[PATCH 2] PNP: Work around BIOS defects in Intel MCH area reporting

2014-04-21 Thread Bjorn Helgaas
Work around BIOSes that don't report the entire Intel MCH area. MCHBAR is not an architected PCI BAR, so MCH space is usually reported as a PNP0C02 resource. The MCH space was once 16KB, but is 32KB in newer parts. Some BIOSes still report a PNP0C02 resource that is only 16KB, which means the res