Re: [PATCH 2/9] perf/x86/intel: Basic support for metrics counters

2019-05-29 Thread Peter Zijlstra
On Wed, May 29, 2019 at 10:40:52AM -0400, Liang, Kan wrote: > On 5/29/2019 3:28 AM, Peter Zijlstra wrote: > > One way would be to make these 48-51 and put BTS as 52, and then you do > > Can we put BTS 47? Sure, it doesn't matter where you put it. It just needs to be a free bit position, the rest

Re: [PATCH 2/9] perf/x86/intel: Basic support for metrics counters

2019-05-29 Thread Liang, Kan
On 5/29/2019 3:28 AM, Peter Zijlstra wrote: On Tue, May 28, 2019 at 02:21:49PM -0400, Liang, Kan wrote: On 5/28/2019 8:15 AM, Peter Zijlstra wrote: On Tue, May 21, 2019 at 02:40:48PM -0700, kan.li...@linux.intel.com wrote: +/* + * We model PERF_METRICS as more magic fixed-mode PMCs, one f

Re: [PATCH 2/9] perf/x86/intel: Basic support for metrics counters

2019-05-29 Thread Peter Zijlstra
On Tue, May 28, 2019 at 02:20:53PM -0400, Liang, Kan wrote: > On 5/28/2019 8:05 AM, Peter Zijlstra wrote: > > On Tue, May 21, 2019 at 02:40:48PM -0700, kan.li...@linux.intel.com wrote: > @@ -2155,9 +2155,19 @@ static void intel_pmu_disable_event(struct perf_event > *event) > retur

Re: [PATCH 2/9] perf/x86/intel: Basic support for metrics counters

2019-05-29 Thread Peter Zijlstra
On Tue, May 28, 2019 at 02:21:49PM -0400, Liang, Kan wrote: > > > On 5/28/2019 8:15 AM, Peter Zijlstra wrote: > > On Tue, May 21, 2019 at 02:40:48PM -0700, kan.li...@linux.intel.com wrote: > > > +/* > > > + * We model PERF_METRICS as more magic fixed-mode PMCs, one for each > > > metric > > > +

Re: [PATCH 2/9] perf/x86/intel: Basic support for metrics counters

2019-05-28 Thread Liang, Kan
On 5/28/2019 8:15 AM, Peter Zijlstra wrote: On Tue, May 21, 2019 at 02:40:48PM -0700, kan.li...@linux.intel.com wrote: +/* + * We model PERF_METRICS as more magic fixed-mode PMCs, one for each metric + * and another for the whole slots counter + * + * Internally they all map to Fixed Ctr 3 (S

Re: [PATCH 2/9] perf/x86/intel: Basic support for metrics counters

2019-05-28 Thread Liang, Kan
On 5/28/2019 8:05 AM, Peter Zijlstra wrote: On Tue, May 21, 2019 at 02:40:48PM -0700, kan.li...@linux.intel.com wrote: From: Andi Kleen Metrics counters (hardware counters containing multiple metrics) are modeled as separate registers for each TopDown metric events, with an extra reg being

Re: [PATCH 2/9] perf/x86/intel: Basic support for metrics counters

2019-05-28 Thread Peter Zijlstra
On Tue, May 21, 2019 at 02:40:48PM -0700, kan.li...@linux.intel.com wrote: > +/* > + * We model PERF_METRICS as more magic fixed-mode PMCs, one for each metric > + * and another for the whole slots counter > + * > + * Internally they all map to Fixed Ctr 3 (SLOTS), and allocate PERF_METRICS > + * a

Re: [PATCH 2/9] perf/x86/intel: Basic support for metrics counters

2019-05-28 Thread Peter Zijlstra
On Tue, May 21, 2019 at 02:40:48PM -0700, kan.li...@linux.intel.com wrote: > From: Andi Kleen > > Metrics counters (hardware counters containing multiple metrics) > are modeled as separate registers for each TopDown metric events, > with an extra reg being used for coordinating access to the > un

[PATCH 2/9] perf/x86/intel: Basic support for metrics counters

2019-05-21 Thread kan . liang
From: Andi Kleen Metrics counters (hardware counters containing multiple metrics) are modeled as separate registers for each TopDown metric events, with an extra reg being used for coordinating access to the underlying register in the scheduler. This patch adds the basic infrastructure to separa