On 04/03/2018 02:40 PM, Maxime Ripard wrote:
On Tue, Apr 03, 2018 at 02:08:43PM +0300, Sergey Suloev wrote:
On 04/03/2018 11:10 AM, Maxime Ripard wrote:
On Thu, Mar 29, 2018 at 09:59:03PM +0300, Sergey Suloev wrote:
There is no need to handle 3/4 empty/full interrupts as the maximum
supported
On Tue, Apr 03, 2018 at 02:08:43PM +0300, Sergey Suloev wrote:
> On 04/03/2018 11:10 AM, Maxime Ripard wrote:
> > On Thu, Mar 29, 2018 at 09:59:03PM +0300, Sergey Suloev wrote:
> > > There is no need to handle 3/4 empty/full interrupts as the maximum
> > > supported transfer length in PIO mode is 6
On 04/03/2018 11:10 AM, Maxime Ripard wrote:
On Thu, Mar 29, 2018 at 09:59:03PM +0300, Sergey Suloev wrote:
There is no need to handle 3/4 empty/full interrupts as the maximum
supported transfer length in PIO mode is 64 bytes for sun4i-family
SoCs.
That assumes that you'll be able to treat the
On 04/03/2018 11:10 AM, Maxime Ripard wrote:
On Thu, Mar 29, 2018 at 09:59:03PM +0300, Sergey Suloev wrote:
There is no need to handle 3/4 empty/full interrupts as the maximum
supported transfer length in PIO mode is 64 bytes for sun4i-family
SoCs.
That assumes that you'll be able to treat the
On Thu, Mar 29, 2018 at 09:59:03PM +0300, Sergey Suloev wrote:
> There is no need to handle 3/4 empty/full interrupts as the maximum
> supported transfer length in PIO mode is 64 bytes for sun4i-family
> SoCs.
That assumes that you'll be able to treat the FIFO full interrupt and
drain the FIFO bef
There is no need to handle 3/4 empty/full interrupts
as the maximum supported transfer length in PIO mode
is 64 bytes for sun4i-family SoCs. As long as a
problem was reported previously with filling FIFO
on A10s then we stick with 63 bytes depth.
Signed-off-by: Sergey Suloev
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drivers/spi/spi
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