On Tue, Jun 06, 2017 at 06:21:08PM +0200, Peter Zijlstra wrote:
> On Tue, Jun 06, 2017 at 06:51:20AM -0700, Andi Kleen wrote:
> > > Not too happy about that..
> > >
> > > P(LVLX, L4) | P(LVLX, REMOTE)
> > >
> > > reads like something that should be PERF_MEM_LVL_REM_CCE1 or something
> >
> > CC
On Tue, Jun 06, 2017 at 06:51:20AM -0700, Andi Kleen wrote:
> > Not too happy about that..
> >
> > P(LVLX, L4) | P(LVLX, REMOTE)
> >
> > reads like something that should be PERF_MEM_LVL_REM_CCE1 or something
>
> CCE1? You mean L4?
#define PERF_MEM_LVL_REM_CCE1 0x400 /* Remote Cache (1 hop)
> Not too happy about that..
>
> P(LVLX, L4) | P(LVLX, REMOTE)
>
> reads like something that should be PERF_MEM_LVL_REM_CCE1 or something
CCE1? You mean L4?
The two bits seem cleaner to me than enumerating all cases. But ok.
REM_L4
> This new generic 'REMOTE' has too much overlap with the
On Mon, Jun 05, 2017 at 03:48:34PM -0700, Andi Kleen wrote:
> +void __init intel_pmu_pebs_data_source_skl(void)
> +{
> + pebs_data_source[0x08] = OP_LH | P(LVLX, L4) | P(SNOOP, HIT);
> + pebs_data_source[0x09] = OP_LH | P(LVLX, L4) | P(LVLX, REMOTE) |
> P(SNOOP, HIT);
> + pebs_data_so
From: Andi Kleen
Skylake changed the encoding of the PEBS data source field.
Some combinations are not available anymore, but some new cases
e.g. for L4 cache hit are added.
Fix up the conversion table for Skylake, similar as had been done
for Nehalem.
To properly describe it in the abstracted
From: Andi Kleen
Skylake changed the encoding of the PEBS data source field.
Some combinations are not available anymore, but some new cases
e.g. for L4 cache hit are added.
Fix up the conversion table for Skylake, similar as had been done
for Nehalem.
To properly describe it in the abstracted
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