Re: [PATCH 2/6] clk: qcom: gdsc: Add support for gdscs with gds hw controller

2015-12-01 Thread Rajendra Nayak
[].. >> >> return -ETIMEDOUT; >> >> } >> >> >> >> @@ -165,6 +169,7 @@ static int gdsc_init(struct gdsc *sc) >> >> { >> >> u32 mask, val; >> >> int on, ret; >> >> + unsigned int reg; >> >> >> >> /* >> >>* Disable HW trigger: collapse/restore occur based on registers >> writes. >> >> @

Re: [PATCH 2/6] clk: qcom: gdsc: Add support for gdscs with gds hw controller

2015-11-30 Thread Stephen Boyd
On 12/01, Rajendra Nayak wrote: > > On 12/01/2015 07:52 AM, Stephen Boyd wrote: > > On 11/26, Rajendra Nayak wrote: > > > >> + udelay(1); > >> + } > >> + > >> + do { > >> + if (gdsc_is_enabled(sc, status_reg) == en) > >>return 0; > >>} while (time_befor

Re: [PATCH 2/6] clk: qcom: gdsc: Add support for gdscs with gds hw controller

2015-11-30 Thread Rajendra Nayak
On 12/01/2015 07:52 AM, Stephen Boyd wrote: > On 11/26, Rajendra Nayak wrote: >> @@ -58,30 +58,34 @@ static int gdsc_toggle_logic(struct gdsc *sc, bool en) >> { >> int ret; >> u32 val = en ? 0 : SW_COLLAPSE_MASK; >> -u32 check = en ? PWR_ON_MASK : 0; >> unsigned long timeout; >

Re: [PATCH 2/6] clk: qcom: gdsc: Add support for gdscs with gds hw controller

2015-11-30 Thread Stephen Boyd
On 11/26, Rajendra Nayak wrote: > @@ -58,30 +58,34 @@ static int gdsc_toggle_logic(struct gdsc *sc, bool en) > { > int ret; > u32 val = en ? 0 : SW_COLLAPSE_MASK; > - u32 check = en ? PWR_ON_MASK : 0; > unsigned long timeout; > + unsigned int status_reg = sc->gdscr; > >

[PATCH 2/6] clk: qcom: gdsc: Add support for gdscs with gds hw controller

2015-11-25 Thread Rajendra Nayak
Some gdsc power domains can have a gds_hw_controller block inside to help ensure all slave devices within the power domain are idle before the gdsc is actually switched off. This is mainly useful in power domains which host a MMU, in which case its necessary to make sure there are no outstanding MM