* Peter Zijlstra wrote:
> > > I yelled at BIOS engineers over their PMU usage and $vendor
> > > added a BIOS knob to disable that, I'll yell at BIOS engineers
> > > again, just give me their number.
> > >
> > > Really, say NO already.
> >
> > Ok, so no technical reason, merely a "me vs you"
On Fri, Aug 01, 2014 at 03:21:20PM +0200, Andi Kleen wrote:
> > > NAK!
> > >
> > > I already said this isn't going to ever happen.
> > >
> > > Both PT and LBR are arbitrated through the kernel, therefore we can (and
> > > must) deny PT when there's existing LBR usage and vice versa.
> > >
> > >
> > NAK!
> >
> > I already said this isn't going to ever happen.
> >
> > Both PT and LBR are arbitrated through the kernel, therefore we can (and
> > must) deny PT when there's existing LBR usage and vice versa.
> >
> > We will not hijack resources like this full stop end of story.
> >
> > Fuck
On Fri, Aug 01, 2014 at 09:38:25AM +0200, Peter Zijlstra wrote:
> On Thu, Jul 31, 2014 at 02:41:02AM -0700, kan.li...@intel.com wrote:
> > From: Kan Liang
> >
> > Intel PT will take over LBR hardware. If RTIT_CTL.TraceEn=1, any attempt to
> > read or write the LBR or LER MSRs, including LBR_TOS,
On Thu, Jul 31, 2014 at 02:41:02AM -0700, kan.li...@intel.com wrote:
> From: Kan Liang
>
> Intel PT will take over LBR hardware. If RTIT_CTL.TraceEn=1, any attempt to
> read or write the LBR or LER MSRs, including LBR_TOS, will result in a #GP.
> Intel PT can be enabled/disabled at runtime by har
From: Kan Liang
Intel PT will take over LBR hardware. If RTIT_CTL.TraceEn=1, any attempt to
read or write the LBR or LER MSRs, including LBR_TOS, will result in a #GP.
Intel PT can be enabled/disabled at runtime by hardware/BIOS, so it's better
LBR MSRs can be protected at runtime.
The {rd,wr}ms
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