On Tue, Aug 07, 2018 at 11:29:54AM -0400, Liang, Kan wrote:
> On 8/6/2018 2:35 PM, Peter Zijlstra wrote:
> > On Mon, Aug 06, 2018 at 10:23:42AM -0700, kan.li...@linux.intel.com wrote:
> > > @@ -2044,6 +2056,14 @@ static void intel_pmu_disable_event(struct
> > > perf_event *event)
> > > i
On 8/6/2018 2:35 PM, Peter Zijlstra wrote:
On Mon, Aug 06, 2018 at 10:23:42AM -0700, kan.li...@linux.intel.com wrote:
@@ -2044,6 +2056,14 @@ static void intel_pmu_disable_event(struct perf_event
*event)
if (unlikely(event->attr.precise_ip))
intel_pmu_pebs_disable(even
On Mon, Aug 06, 2018 at 02:33:23PM -0700, Andi Kleen wrote:
> On Mon, Aug 06, 2018 at 08:35:15PM +0200, Peter Zijlstra wrote:
> > > +static bool disable_counter_freezing;
> > > +module_param(disable_counter_freezing, bool, 0444);
> > > +MODULE_PARM_DESC(disable_counter_freezing, "Disable counter fr
On Mon, Aug 06, 2018 at 08:35:15PM +0200, Peter Zijlstra wrote:
> > +static bool disable_counter_freezing;
> > +module_param(disable_counter_freezing, bool, 0444);
> > +MODULE_PARM_DESC(disable_counter_freezing, "Disable counter freezing
> > feature."
> > + "The PMI handler will fall bac
On Mon, Aug 06, 2018 at 10:23:42AM -0700, kan.li...@linux.intel.com wrote:
> @@ -2044,6 +2056,14 @@ static void intel_pmu_disable_event(struct perf_event
> *event)
> if (unlikely(event->attr.precise_ip))
> intel_pmu_pebs_disable(event);
>
> + /*
> + * We could disabl
From: Andi Kleen
Implements counter freezing for Arch Perfmon v4 (Skylake and
newer). This allows to speed up the PMI handler by avoiding
unnecessary MSR writes and make it more accurate.
The Arch Perfmon v4 PMI handler is substantially different than
the older PMI handler.
Differences to the o
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