On Fri, 9 Apr 2021, Wu, Hao wrote:
On Fri, Apr 09, 2021 at 12:02:47PM +0800, Wu, Hao wrote:
+
+static void dfl_spi_altera_remove(struct dfl_device *dfl_dev)
+{
+struct dfl_altera_spi *aspi = dev_get_drvdata(&dfl_dev->dev);
+
+platform_device_unregister(aspi->altr_spi);
+}
+
+#define FME_FEAT
> On Fri, Apr 09, 2021 at 12:02:47PM +0800, Wu, Hao wrote:
> > > > > > > > > > +
> > > > > > > > > > +static void dfl_spi_altera_remove(struct dfl_device
> > > > > > > > > > *dfl_dev)
> > > > > > > > > > +{
> > > > > > > > > > +struct dfl_altera_spi *aspi =
> > > > > > > > > > dev_get_drvdata(&df
On Fri, Apr 09, 2021 at 12:02:47PM +0800, Wu, Hao wrote:
> > > > > > > > > +
> > > > > > > > > +static void dfl_spi_altera_remove(struct dfl_device *dfl_dev)
> > > > > > > > > +{
> > > > > > > > > +struct dfl_altera_spi *aspi = dev_get_drvdata(&dfl_dev->dev);
> > > > > > > > > +
> > > > > > > > > +
> > > > > > > > +
> > > > > > > > +static void dfl_spi_altera_remove(struct dfl_device *dfl_dev)
> > > > > > > > +{
> > > > > > > > +struct dfl_altera_spi *aspi = dev_get_drvdata(&dfl_dev->dev);
> > > > > > > > +
> > > > > > > > +platform_device_unregister(aspi->altr_spi);
> > > > > > > > +}
> > >
> On Thu, Apr 08, 2021 at 09:20:19AM +, Wu, Hao wrote:
> > > On Thu, Apr 08, 2021 at 03:30:15PM +0800, Wu, Hao wrote:
> > > > > > On Mon, 5 Apr 2021, Moritz Fischer wrote:
> > > > > >
> > > > > > > Hi Matthew,
> > > > > > >
> > > > > > > On Mon, Apr 05, 2021 at 04:53:00PM -0700,
> > > > > matth
On Thu, Apr 08, 2021 at 11:53:06AM -0700, Moritz Fischer wrote:
> On Thu, Apr 08, 2021 at 09:20:19AM +, Wu, Hao wrote:
> > > On Thu, Apr 08, 2021 at 03:30:15PM +0800, Wu, Hao wrote:
> > > > > > On Mon, 5 Apr 2021, Moritz Fischer wrote:
> > > > > >
> > > > > > > Hi Matthew,
> > > > > > >
> > > >
On Thu, Apr 08, 2021 at 05:20:19PM +0800, Wu, Hao wrote:
> > On Thu, Apr 08, 2021 at 03:30:15PM +0800, Wu, Hao wrote:
> > > > > On Mon, 5 Apr 2021, Moritz Fischer wrote:
> > > > >
> > > > > > Hi Matthew,
> > > > > >
> > > > > > On Mon, Apr 05, 2021 at 04:53:00PM -0700,
> > > > matthew.gerl...@linux
On Thu, Apr 08, 2021 at 09:20:19AM +, Wu, Hao wrote:
> > On Thu, Apr 08, 2021 at 03:30:15PM +0800, Wu, Hao wrote:
> > > > > On Mon, 5 Apr 2021, Moritz Fischer wrote:
> > > > >
> > > > > > Hi Matthew,
> > > > > >
> > > > > > On Mon, Apr 05, 2021 at 04:53:00PM -0700,
> > > > matthew.gerl...@linux
> On Thu, Apr 08, 2021 at 03:30:15PM +0800, Wu, Hao wrote:
> > > > On Mon, 5 Apr 2021, Moritz Fischer wrote:
> > > >
> > > > > Hi Matthew,
> > > > >
> > > > > On Mon, Apr 05, 2021 at 04:53:00PM -0700,
> > > matthew.gerl...@linux.intel.com wrote:
> > > > > > From: Matthew Gerlach
> > > > > >
> > >
On Thu, Apr 08, 2021 at 03:30:15PM +0800, Wu, Hao wrote:
> > > On Mon, 5 Apr 2021, Moritz Fischer wrote:
> > >
> > > > Hi Matthew,
> > > >
> > > > On Mon, Apr 05, 2021 at 04:53:00PM -0700,
> > matthew.gerl...@linux.intel.com wrote:
> > > > > From: Matthew Gerlach
> > > > >
> > > > > This patch add
> > On Mon, 5 Apr 2021, Moritz Fischer wrote:
> >
> > > Hi Matthew,
> > >
> > > On Mon, Apr 05, 2021 at 04:53:00PM -0700,
> matthew.gerl...@linux.intel.com wrote:
> > > > From: Matthew Gerlach
> > > >
> > > > This patch adds DFL bus driver for the Altera SPI Master
> > > > controller. The SPI mas
Hi Matthew,
On Tue, Apr 06, 2021 at 09:05:35AM -0700, matthew.gerl...@linux.intel.com wrote:
>
> Hi Moritz,
>
> On Mon, 5 Apr 2021, Moritz Fischer wrote:
>
> > Hi Matthew,
> >
> > On Mon, Apr 05, 2021 at 04:53:00PM -0700, matthew.gerl...@linux.intel.com
> > wrote:
> > > From: Matthew Gerlach
Hi Moritz,
On Mon, 5 Apr 2021, Moritz Fischer wrote:
Hi Matthew,
On Mon, Apr 05, 2021 at 04:53:00PM -0700, matthew.gerl...@linux.intel.com wrote:
From: Matthew Gerlach
This patch adds DFL bus driver for the Altera SPI Master
controller. The SPI master is connected to an Intel SPI Slave t
Hi Matthew,
On Mon, Apr 05, 2021 at 04:53:00PM -0700, matthew.gerl...@linux.intel.com wrote:
> From: Matthew Gerlach
>
> This patch adds DFL bus driver for the Altera SPI Master
> controller. The SPI master is connected to an Intel SPI Slave to
> Avalon Master Bridge, inside an Intel MAX10 BMC
From: Matthew Gerlach
This patch adds DFL bus driver for the Altera SPI Master
controller. The SPI master is connected to an Intel SPI Slave to
Avalon Master Bridge, inside an Intel MAX10 BMC Chip.
Signed-off-by: Matthew Gerlach
---
drivers/fpga/Kconfig | 9 ++
drivers/fpga/Makefil
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