Re: [PATCH 2/2] x86: extend insn decoder to understand xop and evex prefixes

2014-09-05 Thread Masami Hiramatsu
Hi Denys, (2014/09/04 21:54), Denys Vlasenko wrote: > Since xop and evex prefixes are extensions of vex mechanism, > they have similar bit layouts, and they can never be combined > (an instruction can have only one of them), > (ab)use insn->vex_prefix to store data of xop and evex too. > > Users

[PATCH 2/2] x86: extend insn decoder to understand xop and evex prefixes

2014-09-04 Thread Denys Vlasenko
Since xop and evex prefixes are extensions of vex mechanism, they have similar bit layouts, and they can never be combined (an instruction can have only one of them), (ab)use insn->vex_prefix to store data of xop and evex too. Users will need to conditionalize on insn->vex_prefix.bytes[0] instead

Re: [PATCH 2/2] x86: extend insn decoder to understand xop and evex prefixes

2014-05-21 Thread Masami Hiramatsu
(2014/05/20 0:04), Denys Vlasenko wrote: > On 05/17/2014 06:00 PM, Masami Hiramatsu wrote: >> (2014/05/17 3:34), Denys Vlasenko wrote: >>> Since xop and evex prefixes are extensions of vex mechanism, >>> they have similar bit layouts, and they can never be combined >>> (an instruction can have only

Re: [PATCH 2/2] x86: extend insn decoder to understand xop and evex prefixes

2014-05-19 Thread Denys Vlasenko
On 05/17/2014 06:00 PM, Masami Hiramatsu wrote: > (2014/05/17 3:34), Denys Vlasenko wrote: >> Since xop and evex prefixes are extensions of vex mechanism, >> they have similar bit layouts, and they can never be combined >> (an instruction can have only one of them), >> (ab)use insn->vex_prefix to s

Re: [PATCH 2/2] x86: extend insn decoder to understand xop and evex prefixes

2014-05-17 Thread Masami Hiramatsu
(2014/05/17 3:34), Denys Vlasenko wrote: > Since xop and evex prefixes are extensions of vex mechanism, > they have similar bit layouts, and they can never be combined > (an instruction can have only one of them), > (ab)use insn->vex_prefix to store data of xop and evex too. > > Users will need to

[PATCH 2/2] x86: extend insn decoder to understand xop and evex prefixes

2014-05-16 Thread Denys Vlasenko
Since xop and evex prefixes are extensions of vex mechanism, they have similar bit layouts, and they can never be combined (an instruction can have only one of them), (ab)use insn->vex_prefix to store data of xop and evex too. Users will need to conditionalize on insn->vex_prefix.bytes[0] instead