Hi, jerome
On 2019/10/14 22:55, Jerome Brunet wrote:
On Mon 14 Oct 2019 at 15:42, Jian Hu wrote:
if peripheral clocks probe first, it will fail to get
fixed_pll clocks. A lot of peripheral clocks parent are fclk_div2/3/5/7.
and we can not get fclk_div2/3/5/7 clocks.
What does "fail" mean ?
On Mon 14 Oct 2019 at 15:42, Jian Hu wrote:
>>> if peripheral clocks probe first, it will fail to get
>>> fixed_pll clocks. A lot of peripheral clocks parent are fclk_div2/3/5/7.
>>> and we can not get fclk_div2/3/5/7 clocks.
>>
>> What does "fail" mean ?
>> I intended to get clock using devm_c
Hi, Jerome
sorry, it's my problem.
I did not discribe clearly the issue.
On 2019/10/11 15:39, Jerome Brunet wrote:
On Tue 08 Oct 2019 at 10:03, Jian Hu wrote:
Hi, Jerome
PLL clocks and peripheral clocks rely on each other.
for fixed_pll, we can describe its parent like this:
xtal-->xtal
On Tue 08 Oct 2019 at 10:03, Jian Hu wrote:
> Hi, Jerome
>
> PLL clocks and peripheral clocks rely on each other.
>
> for fixed_pll, we can describe its parent like this:
>
> xtal-->xtal_fixpll-->fixed_dco-->fixed_pll
>
> xtal fixpll is belong to peripheral region.
> fixed_pll/fclk_div2/fclk_di
Hi, Jerome
PLL clocks and peripheral clocks rely on each other.
for fixed_pll, we can describe its parent like this:
xtal-->xtal_fixpll-->fixed_dco-->fixed_pll
xtal fixpll is belong to peripheral region.
fixed_pll/fclk_div2/fclk_div3 is belong to PLL region.
if PLL clocks probe first, it will
On 2019/9/27 21:32, Jerome Brunet wrote:
On Fri 27 Sep 2019 at 11:52, Jian Hu wrote:
Hi, Jerome
Thank you for review.
On 2019/9/25 23:09, Jerome Brunet wrote:
On Wed 25 Sep 2019 at 19:44, Jian Hu wrote:
The Amlogic A1 clock includes three parts:
peripheral clocks, pll clocks, CPU clo
On 2019/9/27 20:56, Jerome Brunet wrote:
On Fri 27 Sep 2019 at 05:11, Jian Hu wrote:
Hi, Stephen
Thank you for review
On 2019/9/25 21:12, Stephen Boyd wrote:
Quoting Jian Hu (2019-09-25 04:44:48)
The Amlogic A1 clock includes three parts:
peripheral clocks, pll clocks, CPU clocks.
sys p
On Fri 27 Sep 2019 at 11:52, Jian Hu wrote:
> Hi, Jerome
>
> Thank you for review.
>
> On 2019/9/25 23:09, Jerome Brunet wrote:
>> On Wed 25 Sep 2019 at 19:44, Jian Hu wrote:
>>
>>> The Amlogic A1 clock includes three parts:
>>> peripheral clocks, pll clocks, CPU clocks.
>>> sys pll and CPU cl
On Fri 27 Sep 2019 at 05:11, Jian Hu wrote:
> Hi, Stephen
>
> Thank you for review
>
> On 2019/9/25 21:12, Stephen Boyd wrote:
>> Quoting Jian Hu (2019-09-25 04:44:48)
>>> The Amlogic A1 clock includes three parts:
>>> peripheral clocks, pll clocks, CPU clocks.
>>> sys pll and CPU clocks will b
Hi, Jerome
Thank you for review.
On 2019/9/25 23:09, Jerome Brunet wrote:
On Wed 25 Sep 2019 at 19:44, Jian Hu wrote:
The Amlogic A1 clock includes three parts:
peripheral clocks, pll clocks, CPU clocks.
sys pll and CPU clocks will be sent in next patch.
Unlike the previous series, there is
Hi, Stephen
Thank you for review
On 2019/9/25 21:12, Stephen Boyd wrote:
Quoting Jian Hu (2019-09-25 04:44:48)
The Amlogic A1 clock includes three parts:
peripheral clocks, pll clocks, CPU clocks.
sys pll and CPU clocks will be sent in next patch.
Unlike the previous series, there is no EE/AO
On Wed 25 Sep 2019 at 19:44, Jian Hu wrote:
> The Amlogic A1 clock includes three parts:
> peripheral clocks, pll clocks, CPU clocks.
> sys pll and CPU clocks will be sent in next patch.
>
> Unlike the previous series, there is no EE/AO domain
> in A1 CLK controllers.
>
> Signed-off-by: Jian Hu
Quoting Jian Hu (2019-09-25 04:44:48)
> The Amlogic A1 clock includes three parts:
> peripheral clocks, pll clocks, CPU clocks.
> sys pll and CPU clocks will be sent in next patch.
>
> Unlike the previous series, there is no EE/AO domain
> in A1 CLK controllers.
>
> Signed-off-by: Jian Hu
> Sign
The Amlogic A1 clock includes three parts:
peripheral clocks, pll clocks, CPU clocks.
sys pll and CPU clocks will be sent in next patch.
Unlike the previous series, there is no EE/AO domain
in A1 CLK controllers.
Signed-off-by: Jian Hu
Signed-off-by: Jianxin Pan
---
arch/arm64/Kconfig.platform
14 matches
Mail list logo
