Re: [PATCH 2/2] arm: Set the page table freeing ceiling to TASK_SIZE

2013-02-19 Thread Catalin Marinas
Hugh, On Tue, Feb 19, 2013 at 06:20:50PM +, Hugh Dickins wrote: > On Mon, 18 Feb 2013, Catalin Marinas wrote: > > > ARM processors with LPAE enabled use 3 levels of page tables, with an > > entry in the top level (pgd) covering 1GB of virtual space. Because of > > the branch relocation limita

Re: [PATCH 2/2] arm: Set the page table freeing ceiling to TASK_SIZE

2013-02-19 Thread Hugh Dickins
On Mon, 18 Feb 2013, Catalin Marinas wrote: > ARM processors with LPAE enabled use 3 levels of page tables, with an > entry in the top level (pgd) covering 1GB of virtual space. Because of > the branch relocation limitations on ARM, the loadable modules are > mapped 16MB below PAGE_OFFSET, making

[PATCH 2/2] arm: Set the page table freeing ceiling to TASK_SIZE

2013-02-18 Thread Catalin Marinas
ARM processors with LPAE enabled use 3 levels of page tables, with an entry in the top level (pgd) covering 1GB of virtual space. Because of the branch relocation limitations on ARM, the loadable modules are mapped 16MB below PAGE_OFFSET, making the corresponding 1GB pgd shared between kernel modul