* Tony Lindgren [170914 16:38]:
> * Linus Walleij [170914 07:00]:
> > On Fri, Sep 1, 2017 at 8:57 PM, Thierry Reding
> > wrote:
> >
> > > From: Thierry Reding
> > >
> > > Some GPIO controllers are subdivided into multiple logical blocks called
> > > banks (or ports). This is often caused by t
* Linus Walleij [170914 07:00]:
> On Fri, Sep 1, 2017 at 8:57 PM, Thierry Reding
> wrote:
>
> > From: Thierry Reding
> >
> > Some GPIO controllers are subdivided into multiple logical blocks called
> > banks (or ports). This is often caused by the design assigning separate
> > resources, such
On Fri, Sep 1, 2017 at 8:57 PM, Thierry Reding wrote:
> From: Thierry Reding
>
> Some GPIO controllers are subdivided into multiple logical blocks called
> banks (or ports). This is often caused by the design assigning separate
> resources, such as register regions or interrupts, to each bank, o
From: Thierry Reding
Some GPIO controllers are subdivided into multiple logical blocks called
banks (or ports). This is often caused by the design assigning separate
resources, such as register regions or interrupts, to each bank, or some
set of banks.
This commit adds support for describing con
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