On Fri, Mar 22, 2019 at 12:04:55PM -0700, Stephane Eranian wrote:
> On Thu, Mar 21, 2019 at 10:51 AM Thomas Gleixner wrote:
> >
> > On Thu, 21 Mar 2019, Stephane Eranian wrote:
> > > On Thu, Mar 21, 2019 at 9:45 AM Thomas Gleixner
> > > wrote:
> > > >
> > > > On Thu, 21 Mar 2019, Peter Zijlstra
; Ingo Molnar ; Jiri Olsa
; LKML
Subject: RE: [PATCH 1/8] perf/x86/intel: Fix memory corruption
Attached cpu hotplug test output while perf is running in the background. No
WARN messages seen.
When I run the kexec command, it boots to bios. Haven't used kexec before.
Still trying to f
On Thu, Mar 21, 2019 at 10:51 AM Thomas Gleixner wrote:
>
> On Thu, 21 Mar 2019, Stephane Eranian wrote:
> > On Thu, Mar 21, 2019 at 9:45 AM Thomas Gleixner wrote:
> > >
> > > On Thu, 21 Mar 2019, Peter Zijlstra wrote:
> > > > Subject: perf/x86/intel: Initialize TFA MSR
> > > >
> > > > Stephane r
Sent: Thursday, March 21, 2019 1:07 PM
To: DSouza, Nelson
Cc: Tony Jones ; Thomas Gleixner ; Stephane
Eranian ; Ingo Molnar ; Jiri Olsa
; LKML
Subject: Re: [PATCH 1/8] perf/x86/intel: Fix memory corruption
On Thu, Mar 21, 2019 at 07:47:50PM +, DSouza, Nelson wrote:
> Is the request
On Thu, Mar 21, 2019 at 07:47:50PM +, DSouza, Nelson wrote:
> Is the request to check whether the msr gets reset to default upon reboot of
> the machine ?
basically:
- apply patch
- start workload with 4 counter (on all CPUs), such that tfa-msr=1
- try the following:
o cpu hotplug
o
; DSouza, Nelson
Subject: Re: [PATCH 1/8] perf/x86/intel: Fix memory corruption
On 3/21/19 11:20 AM, Peter Zijlstra wrote:
> Might be best to have someone test this.. someone with ucode and a
> machine etc.. :-)
If your own company can't oblige you here Peter :-) I'm sure I can ma
On 3/21/19 11:20 AM, Peter Zijlstra wrote:
> Might be best to have someone test this.. someone with ucode and a
> machine etc.. :-)
If your own company can't oblige you here Peter :-) I'm sure I can make some
time to test it.
On Thu, Mar 21, 2019 at 06:17:01PM +0100, Thomas Gleixner wrote:
> On Thu, 21 Mar 2019, Peter Zijlstra wrote:
> > On Thu, Mar 21, 2019 at 05:45:41PM +0100, Thomas Gleixner wrote:
> > > On Thu, 21 Mar 2019, Peter Zijlstra wrote:
> > > > Subject: perf/x86/intel: Initialize TFA MSR
> > > >
> > > > St
On Thu, 21 Mar 2019, Stephane Eranian wrote:
> On Thu, Mar 21, 2019 at 9:45 AM Thomas Gleixner wrote:
> >
> > On Thu, 21 Mar 2019, Peter Zijlstra wrote:
> > > Subject: perf/x86/intel: Initialize TFA MSR
> > >
> > > Stephane reported that we don't initialize the TFA MSR, which could lead
> > > to t
On Thu, Mar 21, 2019 at 9:45 AM Thomas Gleixner wrote:
>
> On Thu, 21 Mar 2019, Peter Zijlstra wrote:
> > Subject: perf/x86/intel: Initialize TFA MSR
> >
> > Stephane reported that we don't initialize the TFA MSR, which could lead
> > to trouble if the RESET value is not 0 or on kexec.
>
> That se
On Thu, 21 Mar 2019, Peter Zijlstra wrote:
> On Thu, Mar 21, 2019 at 05:45:41PM +0100, Thomas Gleixner wrote:
> > On Thu, 21 Mar 2019, Peter Zijlstra wrote:
> > > Subject: perf/x86/intel: Initialize TFA MSR
> > >
> > > Stephane reported that we don't initialize the TFA MSR, which could lead
> > >
On Thu, Mar 21, 2019 at 05:45:41PM +0100, Thomas Gleixner wrote:
> On Thu, 21 Mar 2019, Peter Zijlstra wrote:
> > Subject: perf/x86/intel: Initialize TFA MSR
> >
> > Stephane reported that we don't initialize the TFA MSR, which could lead
> > to trouble if the RESET value is not 0 or on kexec.
>
On Thu, 21 Mar 2019, Peter Zijlstra wrote:
> Subject: perf/x86/intel: Initialize TFA MSR
>
> Stephane reported that we don't initialize the TFA MSR, which could lead
> to trouble if the RESET value is not 0 or on kexec.
That sentence doesn't parse.
Stephane reported that the TFA MSR is not ini
On Wed, Mar 20, 2019 at 11:22:20PM +0100, Peter Zijlstra wrote:
> On Wed, Mar 20, 2019 at 01:47:28PM -0700, Stephane Eranian wrote:
>
> > Right now, if I do:
> >
> > echo 0 > /sys/bus/event_source/devices/cpu/allow_tsx_force_abort
> >
> > Then I don't have the guarantee on when there will be no
On Wed, Mar 20, 2019 at 01:47:28PM -0700, Stephane Eranian wrote:
> Right now, if I do:
>
> echo 0 > /sys/bus/event_source/devices/cpu/allow_tsx_force_abort
>
> Then I don't have the guarantee on when there will be no abort when I
> return from the echo. the MSR is accessed only on PMU scheduli
On Wed, Mar 20, 2019 at 1:47 PM Stephane Eranian wrote:
>
> On Tue, Mar 19, 2019 at 11:20 AM Peter Zijlstra wrote:
> >
> > On Tue, Mar 19, 2019 at 10:52:01AM -0700, Stephane Eranian wrote:
> > > > Not quite; the control on its own doesn't directly write the MSR. And
> > > > even when the work-aro
On Tue, Mar 19, 2019 at 11:20 AM Peter Zijlstra wrote:
>
> On Tue, Mar 19, 2019 at 10:52:01AM -0700, Stephane Eranian wrote:
> > > Not quite; the control on its own doesn't directly write the MSR. And
> > > even when the work-around is allowed, we'll not set the MSR unless there
> > > is also dema
On Tue, Mar 19, 2019 at 10:52:01AM -0700, Stephane Eranian wrote:
> > Not quite; the control on its own doesn't directly write the MSR. And
> > even when the work-around is allowed, we'll not set the MSR unless there
> > is also demand for PMC3.
> >
> Trying to understand this better here. When the
On Tue, Mar 19, 2019 at 4:05 AM Peter Zijlstra wrote:
>
> On Mon, Mar 18, 2019 at 11:29:25PM -0700, Stephane Eranian wrote:
>
> > > --- a/arch/x86/events/intel/core.c
> > > +++ b/arch/x86/events/intel/core.c
> > > @@ -3410,7 +3410,7 @@ tfa_get_event_constraints(struct cpu_hw_
> > > /*
> >
On Mon, Mar 18, 2019 at 11:29:25PM -0700, Stephane Eranian wrote:
> > --- a/arch/x86/events/intel/core.c
> > +++ b/arch/x86/events/intel/core.c
> > @@ -3410,7 +3410,7 @@ tfa_get_event_constraints(struct cpu_hw_
> > /*
> > * Without TFA we must not use PMC3.
> > */
> > -
On Thu, Mar 14, 2019 at 6:11 AM Peter Zijlstra wrote:
>
> Through:
>
> validate_event()
> x86_pmu.get_event_constraints(.idx=-1)
> tfa_get_event_constraints()
> dyn_constraint()
>
> We use cpuc->constraint_list[-1], which is an obvious out-of-bound
> access.
>
> In this case, s
Through:
validate_event()
x86_pmu.get_event_constraints(.idx=-1)
tfa_get_event_constraints()
dyn_constraint()
We use cpuc->constraint_list[-1], which is an obvious out-of-bound
access.
In this case, simply skip the TFA constraint code, there is no event
constraint with just P
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