On Mon, May 09, 2016 at 06:14:30PM +0530, Abhishek Sahu wrote:
> 1. Current QCOM I2C driver hangs when sending data to address 0x03-0x07
> in some scenarios. The QUP controller generates invalid write in this
> case, since these addresses are reserved for different bus formats.
>
> 2. Also, the er
On 2016-06-18 22:02, Wolfram Sang wrote:
We run the command i2cdetect for address 0x3 to 0x77. The QUP
generates
write error for address 0x3 to 0x7 apart from other bus errors since
these are reserved addresses. I was getting the crash in non DMA mode
and BAM hang in DMA mode before putting the
> We run the command i2cdetect for address 0x3 to 0x77. The QUP generates
> write error for address 0x3 to 0x7 apart from other bus errors since
> these are reserved addresses. I was getting the crash in non DMA mode
> and BAM hang in DMA mode before putting the fix.
>
> Also we have connected the
On Thu, May 12, 2016 at 03:05:39PM -0500, Andy Gross wrote:
> On 12 May 2016 at 14:32, Abhishek Sahu wrote:
> > On Thu, May 12, 2016 at 12:58:30PM -0500, Andy Gross wrote:
> >> On Thu, May 12, 2016 at 11:48:43AM +0530, Abhishek Sahu wrote:
> >> > On Thu, May 12, 2016 at 12:13:47AM -0500, Andy Gros
On 12 May 2016 at 14:32, Abhishek Sahu wrote:
> On Thu, May 12, 2016 at 12:58:30PM -0500, Andy Gross wrote:
>> On Thu, May 12, 2016 at 11:48:43AM +0530, Abhishek Sahu wrote:
>> > On Thu, May 12, 2016 at 12:13:47AM -0500, Andy Gross wrote:
>> > > On Wed, May 11, 2016 at 11:04:17PM +0530, Abhishek S
On Thu, May 12, 2016 at 12:58:30PM -0500, Andy Gross wrote:
> On Thu, May 12, 2016 at 11:48:43AM +0530, Abhishek Sahu wrote:
> > On Thu, May 12, 2016 at 12:13:47AM -0500, Andy Gross wrote:
> > > On Wed, May 11, 2016 at 11:04:17PM +0530, Abhishek Sahu wrote:
> > >
> > >
> > >
> > > > > In q
On Thu, May 12, 2016 at 11:48:43AM +0530, Abhishek Sahu wrote:
> On Thu, May 12, 2016 at 12:13:47AM -0500, Andy Gross wrote:
> > On Wed, May 11, 2016 at 11:04:17PM +0530, Abhishek Sahu wrote:
> >
> >
> >
> > > > In qup_i2c_xfer and qup_i2c_xfer_v2 state is set to RESET at the
> > > >end, w
On Thu, May 12, 2016 at 12:13:47AM -0500, Andy Gross wrote:
> On Wed, May 11, 2016 at 11:04:17PM +0530, Abhishek Sahu wrote:
>
>
>
> > > In qup_i2c_xfer and qup_i2c_xfer_v2 state is set to RESET at the
> > >end, when
> > > there is no error. So would it be fine if we do it there
> >
On Wed, May 11, 2016 at 11:04:17PM +0530, Abhishek Sahu wrote:
> > In qup_i2c_xfer and qup_i2c_xfer_v2 state is set to RESET at the
> >end, when
> > there is no error. So would it be fine if we do it there
> >unconditionally ?
> >
> >Regards,
> > Sricharan
>
> RESET the QUP state wo
vger.kernel.org; ntel...@codeaurora.org; linux-
> ker...@vger.kernel.org; dmaeng...@vger.kernel.org; linux-
> i...@vger.kernel.org; agr...@codeaurora.org; andy.gr...@linaro.org; linux-
> arm-ker...@lists.infradead.org
> Subject: RE: [PATCH 1/2] i2c: qup: Cleared the error bits in ISR
>
&g
On 2016-05-11 21:27, Sricharan wrote:
Hi,
1. Current QCOM I2C driver hangs when sending data to address
0x03-0x07
in some scenarios. The QUP controller generates invalid write in this
case,
since these addresses are reserved for different bus formats.
2. Also, the error handling is done by I2
Hi,
> 1. Current QCOM I2C driver hangs when sending data to address 0x03-0x07
> in some scenarios. The QUP controller generates invalid write in this
case,
> since these addresses are reserved for different bus formats.
>
> 2. Also, the error handling is done by I2C QUP ISR in the case of DMA
mod
1. Current QCOM I2C driver hangs when sending data to address 0x03-0x07
in some scenarios. The QUP controller generates invalid write in this
case, since these addresses are reserved for different bus formats.
2. Also, the error handling is done by I2C QUP ISR in the case of DMA
mode. The state ne
13 matches
Mail list logo
