On 07/02/18 12:34, Dave Martin wrote:
On Wed, Feb 07, 2018 at 11:41:17AM +, Suzuki K Poulose wrote:
On 07/02/18 10:40, Dave Martin wrote:
...
To summarise, I can add LOR/HPD changes. But the others requires a bit more
work and can be done as a separate series.
I've wondered in the past
On Wed, Feb 07, 2018 at 11:41:17AM +, Suzuki K Poulose wrote:
> On 07/02/18 10:40, Dave Martin wrote:
> >On Thu, Feb 01, 2018 at 10:38:37AM +, Suzuki K Poulose wrote:
> >>We treat most of the feature bits in the ID registers as STRICT,
> >>implying that all CPUs should match it the boot CPU
On 07/02/18 10:40, Dave Martin wrote:
On Thu, Feb 01, 2018 at 10:38:37AM +, Suzuki K Poulose wrote:
We treat most of the feature bits in the ID registers as STRICT,
implying that all CPUs should match it the boot CPU state. However,
for most of the features, we can handle if there are any mi
On Thu, Feb 01, 2018 at 10:38:37AM +, Suzuki K Poulose wrote:
> We treat most of the feature bits in the ID registers as STRICT,
> implying that all CPUs should match it the boot CPU state. However,
> for most of the features, we can handle if there are any mismatches
> by using the safe value.
We treat most of the feature bits in the ID registers as STRICT,
implying that all CPUs should match it the boot CPU state. However,
for most of the features, we can handle if there are any mismatches
by using the safe value. e.g, HWCAPs and other features used by the
kernel. Relax the constraint o
5 matches
Mail list logo
