Re: [PATCH 1/2] Add support for Cadence XSPI controller

2020-12-12 Thread Lukas Wunner
On Wed, Dec 09, 2020 at 08:57:57AM +0100, Jayshri Pawar wrote: > + master = spi_alloc_master(dev, sizeof(*cdns_xspi)); > + if (!master) { > + ret = -ENOMEM; > + dev_err(dev, "Failed to allocate memory for spi_master\n"); > + goto err_no_mem; > + } Pl

Re: [PATCH 1/2] Add support for Cadence XSPI controller

2020-12-10 Thread kernel test robot
Hi Jayshri, Thank you for the patch! Perhaps something to improve: [auto build test WARNING on spi/for-next] [also build test WARNING on v5.10-rc7 next-20201209] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as docume

Re: [PATCH 1/2] Add support for Cadence XSPI controller

2020-12-09 Thread kernel test robot
Hi Jayshri, Thank you for the patch! Perhaps something to improve: [auto build test WARNING on spi/for-next] [also build test WARNING on v5.10-rc7 next-20201208] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as docume

[PATCH 1/2] Add support for Cadence XSPI controller

2020-12-09 Thread Jayshri Pawar
This driver uses SPI-MEM framework and is capable to operate with single, dual, quad and octal SPI-NOR memories. Low-level controller work mode (STIG) is utilized to communicate with flash memories. Signed-off-by: Jayshri Pawar Signed-off-by: Konrad Kociolek --- drivers/spi/Kconfig|