Hi Bjorn,
On Wed, Jul 10, 2019 at 5:09 PM Vivek Gautam
wrote:
>
> From: Sai Prakash Ranjan
>
> Last level cache (aka. system cache) controller provides control
> over the last level cache present on SDM845. This cache lies after
> the memory noc, right before the DDR.
>
> Signed-off-by: Sai Prak
From: Sai Prakash Ranjan
Last level cache (aka. system cache) controller provides control
over the last level cache present on SDM845. This cache lies after
the memory noc, right before the DDR.
Signed-off-by: Sai Prakash Ranjan
Signed-off-by: Vivek Gautam
---
arch/arm64/boot/dts/qcom/sdm845.
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