Re: [PATCH 07/15] riscv: implement remote sfence.i using IPIs

On Thu, Oct 17, 2019 at 11:08 PM Christoph Hellwig wrote: > > The RISC-V ISA only supports flushing the instruction cache for the > local CPU core. Currently we always offload the remote TLB flushing to > the SBI, which then issues an IPI under the hoods. But with M-mode > we do not have an SBI

[PATCH 07/15] riscv: implement remote sfence.i using IPIs

The RISC-V ISA only supports flushing the instruction cache for the local CPU core. Currently we always offload the remote TLB flushing to the SBI, which then issues an IPI under the hoods. But with M-mode we do not have an SBI so we have to do it ourselves. IPI to the other nodes using the exi