Re: [PATCH 06/12] gpio: Add Aspeed driver

2016-08-11 Thread Andrew Jeffery
On Thu, 2016-08-11 at 11:20 +0200, Linus Walleij wrote: > On Wed, Jul 20, 2016 at 7:58 AM, Andrew Jeffery > wrote: > > > > > diff --git a/arch/arm/mach-aspeed/Kconfig b/arch/arm/mach- > > aspeed/Kconfig > > index 25a0ae01429e..a52de9d3adfb 100644 > > --- a/arch/arm/mach-aspeed/Kconfig > > +++ b/

Re: [PATCH 06/12] gpio: Add Aspeed driver

2016-08-11 Thread Linus Walleij
On Wed, Jul 20, 2016 at 7:58 AM, Andrew Jeffery wrote: > diff --git a/arch/arm/mach-aspeed/Kconfig b/arch/arm/mach-aspeed/Kconfig > index 25a0ae01429e..a52de9d3adfb 100644 > --- a/arch/arm/mach-aspeed/Kconfig > +++ b/arch/arm/mach-aspeed/Kconfig > @@ -6,6 +6,10 @@ menuconfig ARCH_ASPEED >

Re: [PATCH 06/12] gpio: Add Aspeed driver

2016-07-21 Thread Andrew Jeffery
On Thu, 2016-07-21 at 16:12 -0400, Paul Gortmaker wrote: > On Wed, Jul 20, 2016 at 1:58 AM, Andrew Jeffery wrote: > > > > From: Joel Stanley > > > > The Aspeed SoCs contain GPIOs grouped by letter, where each letter group > > contains 8 pins. The GPIO letter groups are then banked in sets of fo

Re: [PATCH 06/12] gpio: Add Aspeed driver

2016-07-21 Thread Paul Gortmaker
On Wed, Jul 20, 2016 at 1:58 AM, Andrew Jeffery wrote: > From: Joel Stanley > > The Aspeed SoCs contain GPIOs grouped by letter, where each letter group > contains 8 pins. The GPIO letter groups are then banked in sets of four > in the register layout. > > The implementation exposes multiple bank

[PATCH 06/12] gpio: Add Aspeed driver

2016-07-19 Thread Andrew Jeffery
From: Joel Stanley The Aspeed SoCs contain GPIOs grouped by letter, where each letter group contains 8 pins. The GPIO letter groups are then banked in sets of four in the register layout. The implementation exposes multiple banks through the one driver, and requests and releases pins via the pin