On Thu, Apr 10, 2014 at 4:10 PM, Maxime Ripard
wrote:
> On Thu, Apr 10, 2014 at 12:27:32AM +0800, Chen-Yu Tsai wrote:
>> >> > Let me know if these changes are too intrusive.
>> >>
>> >> I wonder if we should do a separate driver for the new PIO controller.
>> >> Clearly it's a separate IP block, w
On Thu, Apr 10, 2014 at 01:14:26AM +0800, Chen-Yu Tsai wrote:
> > 3) other things I haven't noticed yet :-)
>
> Reworking EINT to use one interrupt per bank will yield some more surprises.
>
> There's also new gpiolib irqchip helpers, but that will require reworking
> each pin bank into separate
On Thu, Apr 10, 2014 at 12:27:32AM +0800, Chen-Yu Tsai wrote:
> >> > Let me know if these changes are too intrusive.
> >>
> >> I wonder if we should do a separate driver for the new PIO controller.
> >> Clearly it's a separate IP block, with it's own clock and reset controls.
> >
> > It's been merg
On 09/04/2014 19:14, Chen-Yu Tsai wrote:
> On Thu, Apr 10, 2014 at 12:14 AM, Boris BREZILLON
> wrote:
>> On 09/04/2014 16:53, Chen-Yu Tsai wrote:
>>> Hi Boris,
>>>
>>> On Wed, Apr 9, 2014 at 9:51 PM, Boris BREZILLON
>>> wrote:
Hello,
This series rework the sunxi pinctrl driver to
On Thu, Apr 10, 2014 at 12:14 AM, Boris BREZILLON
wrote:
>
> On 09/04/2014 16:53, Chen-Yu Tsai wrote:
>> Hi Boris,
>>
>> On Wed, Apr 9, 2014 at 9:51 PM, Boris BREZILLON
>> wrote:
>>> Hello,
>>>
>>> This series rework the sunxi pinctrl driver to support the PLx pins
>>> available on the A31 SoC.
>
Hi,
On Wed, Apr 9, 2014 at 11:17 PM, Maxime Ripard
wrote:
> On Wed, Apr 09, 2014 at 10:53:13PM +0800, Chen-Yu Tsai wrote:
>> Hi Boris,
>>
>> On Wed, Apr 9, 2014 at 9:51 PM, Boris BREZILLON
>> wrote:
>> > Hello,
>> >
>> > This series rework the sunxi pinctrl driver to support the PLx pins
>> > av
On 09/04/2014 16:53, Chen-Yu Tsai wrote:
> Hi Boris,
>
> On Wed, Apr 9, 2014 at 9:51 PM, Boris BREZILLON
> wrote:
>> Hello,
>>
>> This series rework the sunxi pinctrl driver to support the PLx pins
>> available on the A31 SoC.
> Thanks for working on this. I mentioned to Maxime on IRC yesterday t
On Wed, Apr 09, 2014 at 05:17:47PM +0200, Maxime Ripard wrote:
> > I have started to document the PRCM block: http://linux-sunxi.org/PRCM
>
> It's quite different on the A31 and on the A23 actually :(
>
> You don't have any of the audio thing for example, but you have the
> CPUs power clamp contr
On Wed, Apr 09, 2014 at 10:53:13PM +0800, Chen-Yu Tsai wrote:
> Hi Boris,
>
> On Wed, Apr 9, 2014 at 9:51 PM, Boris BREZILLON
> wrote:
> > Hello,
> >
> > This series rework the sunxi pinctrl driver to support the PLx pins
> > available on the A31 SoC.
>
> Thanks for working on this. I mentioned
Hi Boris,
On Wed, Apr 9, 2014 at 9:51 PM, Boris BREZILLON
wrote:
> Hello,
>
> This series rework the sunxi pinctrl driver to support the PLx pins
> available on the A31 SoC.
Thanks for working on this. I mentioned to Maxime on IRC yesterday that
we have complete pinctrl drivers for both A31 and
Hello,
This series rework the sunxi pinctrl driver to support the PLx pins
available on the A31 SoC.
It also add missing A31 reset controller DT bindings documentation.
I need those PL pins (actually I only need PL0 and PL1) to support
the P2WI bus, which in turn is used to communicate with the
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