On Tuesday, September 30, 2014 01:42:05 PM Shreyas B Prabhu wrote:
> Hi Rafael,
>
> On Tuesday 30 September 2014 04:58 AM, Rafael J. Wysocki wrote:
> > On Monday, September 29, 2014 03:53:06 PM Shreyas B Prabhu wrote:
> >> Hi,
> >> Any updates on this patch series?
> >
> > I have a couple of patc
Hi Rafael,
On Tuesday 30 September 2014 04:58 AM, Rafael J. Wysocki wrote:
> On Monday, September 29, 2014 03:53:06 PM Shreyas B Prabhu wrote:
>> Hi,
>> Any updates on this patch series?
>
> I have a couple of patches from there in my tree it seems. Please have a look
> at linux-pm.git/linux-nex
On Monday, September 29, 2014 03:53:06 PM Shreyas B Prabhu wrote:
> Hi,
> Any updates on this patch series?
I have a couple of patches from there in my tree it seems. Please have a look
at linux-pm.git/linux-next and please let me know if that's the case.
> On Thursday 18 September 2014 08:41 A
Hi,
Any updates on this patch series?
On Thursday 18 September 2014 08:41 AM, Shreyas B Prabhu wrote:
> Hi,
>
> In this patch series we use winkle for offlined cores. I successfully
> tested the working of this with subcore functionality.
>
> Test scenario was as follows:
> 1. Set SMT mode to 1,
Hi,
In this patch series we use winkle for offlined cores. I successfully
tested the working of this with subcore functionality.
Test scenario was as follows:
1. Set SMT mode to 1, Set subores-per-core to 1
2. Offline a core, in this case cpu 32 (sending it to winkle)
3. Set subcores-per-core to
Hi,
Any updates on this patch series?
On Monday 25 August 2014 11:31 PM, Shreyas B. Prabhu wrote:
> Fast sleep is an idle state, where the core and the L1 and L2
> caches are brought down to a threshold voltage. This also means that
> the communication between L2 and L3 caches have to be fenced. H
Fast sleep is an idle state, where the core and the L1 and L2
caches are brought down to a threshold voltage. This also means that
the communication between L2 and L3 caches have to be fenced. However
the current P8 chips have a bug wherein this fencing between L2 and
L3 caches get delayed by a cpu
Fast sleep is an idle state, where the core and the L1 and L2
caches are brought down to a threshold voltage. This also means that
the communication between L2 and L3 caches have to be fenced. However
the current P8 chips have a bug wherein this fencing between L2 and
L3 caches get delayed by a cpu
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