On 16.02.2015 04:37, Jisheng Zhang wrote:
On Fri, 13 Feb 2015 08:42:54 -0800
Antoine Tenart wrote:
Marvell Berlin SoCs have a chip control register set providing several
individual registers dealing with various controllers (pinctrl, reset,
clk). This chip controller is described by a single DT
Hi all,
On Sun, 15 Feb 2015 19:37:38 -0800
Jisheng Zhang wrote:
> Hi all,
>
> On Fri, 13 Feb 2015 08:42:54 -0800
> Antoine Tenart wrote:
>
> > Hi,
> >
> > Marvell Berlin SoCs have a chip control register set providing several
> > individual registers dealing with various controllers (pinctrl
Hi all,
On Fri, 13 Feb 2015 08:42:54 -0800
Antoine Tenart wrote:
> Hi,
>
> Marvell Berlin SoCs have a chip control register set providing several
> individual registers dealing with various controllers (pinctrl, reset,
> clk). This chip controller is described by a single DT node since the
> in
> >DT bindings of this platform as "unstable", just like the AT91 guys did
> >for their DT bindings
> >(http://git.kernel.org/cgit/linux/kernel/git/next/linux-next.git/tree/Documentation/arm/Atmel/README#n100)
> > ?
>
> Sounds like a plan.
So we all seem to agree that we should break backwards co
On 13.02.2015 19:19, Thomas Petazzoni wrote:
On Fri, 13 Feb 2015 18:31:21 +0100, Andrew Lunn wrote:
Something which needs to be discussed for both this patchset and the
previous one, is backwards compatibility of the device tree.
As far as i can see, these changes are not backwards compatible.
Dear Andrew Lunn,
On Fri, 13 Feb 2015 18:31:21 +0100, Andrew Lunn wrote:
> Something which needs to be discussed for both this patchset and the
> previous one, is backwards compatibility of the device tree.
>
> As far as i can see, these changes are not backwards compatible.
> Somebody trying to
Andrew,
On Fri, Feb 13, 2015 at 06:31:21PM +0100, Andrew Lunn wrote:
> On Fri, Feb 13, 2015 at 05:42:54PM +0100, Antoine Tenart wrote:
> >
> > Marvell Berlin SoCs have a chip control register set providing several
> > individual registers dealing with various controllers (pinctrl, reset,
> > clk)
On Fri, Feb 13, 2015 at 05:42:54PM +0100, Antoine Tenart wrote:
> Hi,
>
> Marvell Berlin SoCs have a chip control register set providing several
> individual registers dealing with various controllers (pinctrl, reset,
> clk). This chip controller is described by a single DT node since the
> indivi
Hi,
Marvell Berlin SoCs have a chip control register set providing several
individual registers dealing with various controllers (pinctrl, reset,
clk). This chip controller is described by a single DT node since the
individual registers are spread among the chip control register bank.
Marvell Ber
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