Re: [PATCH 0/4] Add support for Intel IOMMU 5-level paging

On Wed, Dec 20, 2017 at 11:59:23AM -0800, Sohil Mehta wrote: > Sohil Mehta (4): > iommu/vt-d: Enable upto 57 bits of domain address width > iommu/vt-d: Add a check for 1GB page support > iommu/vt-d: Add a check for 5-level paging support > iommu/vt-d: Enable 5-level paging mode in the PASID

[PATCH 0/4] Add support for Intel IOMMU 5-level paging

Hi All, Upcoming hardware plans to introduce support for 5-level paging[1]. The support for CPU 5-level paging has already been merged in kernel v4.14. The following patches add support for Intel IOMMU 5-level paging. The patches are based on the Intel Virtualization Technology for Directed I/O sp