On Sat, Oct 4, 2014 at 9:17 AM, Leonid Yegoshin
wrote:
> Linus, it works on CPU with hardware page table walker - MIPS P5600 aka
> Apache.
>
> I was involved in architecture development of HTW and took care of it.
Ok, as long as it works architecturally, per-thread TLB fills are fine by me.
Linus, it works on CPU with hardware page table walker - MIPS P5600 aka Apache.
I was involved in architecture development of HTW and took care of it.
Linus Torvalds wrote:
On Sat, Oct 4, 2014 at 1:23 AM, Peter Zijlstra wrote:
> On Fri, Oct 03, 2014 at 08:17:14PM -0700, Leonid Yegoshin wrote
On Sat, Oct 4, 2014 at 1:23 AM, Peter Zijlstra wrote:
> On Fri, Oct 03, 2014 at 08:17:14PM -0700, Leonid Yegoshin wrote:
>> The following series implements an executable stack protection in MIPS.
>>
>> It sets up a per-thread 'VDSO' page and appropriate TLB support.
>
> So traditionally we've alwa
Peter Zijlstra wrote:
>> It sets up a per-thread 'VDSO' page and appropriate TLB support.
> So traditionally we've always avoided per-thread pages like that.
> What makes it worth it on MIPS?
MIPS has branch delay slots - it is an instruction after branch which is
executed
before branch is take
On Fri, Oct 03, 2014 at 08:17:14PM -0700, Leonid Yegoshin wrote:
> The following series implements an executable stack protection in MIPS.
>
> It sets up a per-thread 'VDSO' page and appropriate TLB support.
So traditionally we've always avoided per-thread pages like that. What
makes it worth it
The following series implements an executable stack protection in MIPS.
It sets up a per-thread 'VDSO' page and appropriate TLB support.
Page is set write-protected from user and is maintained via kernel VA.
MIPS FPU emulation is shifted to new page and stack is relieved for
execute protection as
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