On 04/29/2015 02:26 AM, Mika Westerberg wrote:
On Tue, Apr 28, 2015 at 10:36:48AM -0700, sathyanarayanan kuppuswamy wrote:
This requires that the boot firmware (BIOS/coreboot) configures these pins
correctly (input, etc) before handing over to OS. I've tested this on Intel
Baytrail, Braswell a
On Tue, Apr 28, 2015 at 10:36:48AM -0700, sathyanarayanan kuppuswamy wrote:
> >This requires that the boot firmware (BIOS/coreboot) configures these pins
> >correctly (input, etc) before handing over to OS. I've tested this on Intel
> >Baytrail, Braswell and Skylake based machines where this is tru
On 04/28/2015 08:05 AM, Mika Westerberg wrote:
Hi,
Currently drivers for ACPI enumerated devices that have their interrupt
line connected to a GPIO controller instead of IO-APIC are required to do
complete gpiod_get()/gpiod_to_irq() etc. dance themselves. This adds
unnecessary lines of code to
Hi,
Currently drivers for ACPI enumerated devices that have their interrupt
line connected to a GPIO controller instead of IO-APIC are required to do
complete gpiod_get()/gpiod_to_irq() etc. dance themselves. This adds
unnecessary lines of code to these drivers.
It turned out that DT solved the p
4 matches
Mail list logo
