On Sat, 12 Sep 2020 11:17:25 -0700, Douglas Anderson wrote:
> If we're sending bytes over SPI, we know the FIFO is empty at the
> start of the transfer. There's no reason to wait for the interrupt
> telling us to start--we can just start right away. Then if we
> transmit everything in one swell f
On 9/12/2020 11:47 PM, Douglas Anderson wrote:
If we're sending bytes over SPI, we know the FIFO is empty at the
start of the transfer. There's no reason to wait for the interrupt
telling us to start--we can just start right away. Then if we
transmit everything in one swell foop we don't even
On Sat 12 Sep 13:17 CDT 2020, Douglas Anderson wrote:
> If we're sending bytes over SPI, we know the FIFO is empty at the
> start of the transfer. There's no reason to wait for the interrupt
> telling us to start--we can just start right away. Then if we
> transmit everything in one swell foop w
If we're sending bytes over SPI, we know the FIFO is empty at the
start of the transfer. There's no reason to wait for the interrupt
telling us to start--we can just start right away. Then if we
transmit everything in one swell foop we don't even need to bother
listening for TX interrupts.
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