On 2018-08-17 20:29, Mark Brown wrote:
On Fri, Aug 17, 2018 at 04:06:06PM +0530, dk...@codeaurora.org wrote:
Could you please clarify on below query.
I'm not seeing any further questions in your e-mail?
My bad; i mean, you to comment on below explanation on using
cur_speed_hz instead of clk_
On Fri, Aug 17, 2018 at 04:06:06PM +0530, dk...@codeaurora.org wrote:
> Could you please clarify on below query.
I'm not seeing any further questions in your e-mail?
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On 2018-08-14 20:33, Mark Brown wrote:
On Tue, Aug 14, 2018 at 02:30:02PM +0530, dk...@codeaurora.org wrote:
On 2018-08-10 22:16, Mark Brown wrote:
> On Fri, Aug 10, 2018 at 09:59:46PM +0530, dk...@codeaurora.org wrote:
> > delay_usecs is for inter-transfer delays within a message rather than
On Tue, Aug 14, 2018 at 02:30:02PM +0530, dk...@codeaurora.org wrote:
> On 2018-08-10 22:16, Mark Brown wrote:
> > On Fri, Aug 10, 2018 at 09:59:46PM +0530, dk...@codeaurora.org wrote:
> > > delay_usecs is for inter-transfer delays within a message rather than
> > > after the initial chip select a
On 2018-08-10 22:16, Mark Brown wrote:
On Fri, Aug 10, 2018 at 09:59:46PM +0530, dk...@codeaurora.org wrote:
Now the need is, how to communicate the SPI controller maximum
frequency to
SPI core framework?
Is it by DTSI entry or hardcoding in the SPI controller driver?
If you've got a limit t
On Thu, 2018-08-09 at 12:37 -0700, Doug Anderson wrote:
> On Thu, Aug 9, 2018 at 11:24 AM, Trent Piepho wrote:
> >
> I think we're in agreement but perhaps there's a miscommunication here?
>
> I'm saying that we _shouldn't_ put the max-speed of the master in the
> device tree. The max speed for
On Fri, 2018-08-10 at 21:59 +0530, dk...@codeaurora.org wrote:
>
> Here are my couple of cents:
> SPI controller maximum frequency can be lesser than or equal to Clock
> framework's maximum
> frequency, so should not rely on the Clock framework.
But there is probably some means, via the controll
Hi,
On Fri, Aug 10, 2018 at 9:29 AM, wrote:
> Here are my couple of cents:
> SPI controller maximum frequency can be lesser than or equal to Clock
> framework's maximum
> frequency, so should not rely on the Clock framework.
You could make that argument on other SoCs perhaps, but from what I've
Hi,
On Fri, Aug 10, 2018 at 9:43 AM, Mark Brown wrote:
>> IMO the line marked "/* UNNEEDED */" below should be removed:
>
>> ...
>> spi-max-frequency = <5000>; /* UNNEEDED */
>
> This is a line in the device tree (which I agree shouldn't be there),
> not code in the SPI driver?
My w
On Fri, Aug 10, 2018 at 09:59:46PM +0530, dk...@codeaurora.org wrote:
> Now the need is, how to communicate the SPI controller maximum frequency to
> SPI core framework?
> Is it by DTSI entry or hardcoding in the SPI controller driver?
If you've got a limit that exists in the IP the hard code it
On Fri, Aug 10, 2018 at 09:27:05AM -0700, Doug Anderson wrote:
> On Fri, Aug 10, 2018 at 9:13 AM, Mark Brown wrote:
> > On Fri, Aug 10, 2018 at 08:40:17AM -0700, Doug Anderson wrote:
> >> The clock framework should be able to accomplish what you want. If
> >> you just request the rate it will do
On 2018-08-10 21:43, Mark Brown wrote:
On Fri, Aug 10, 2018 at 08:40:17AM -0700, Doug Anderson wrote:
On Fri, Aug 10, 2018 at 3:52 AM, Mark Brown
wrote:
> This is more about matching the data rate between the two drivers - the
> clock framework could (and possibly should) reasonably return a
Hi,
On Fri, Aug 10, 2018 at 9:13 AM, Mark Brown wrote:
> On Fri, Aug 10, 2018 at 08:40:17AM -0700, Doug Anderson wrote:
>> On Fri, Aug 10, 2018 at 3:52 AM, Mark Brown wrote:
>
>> > This is more about matching the data rate between the two drivers - the
>> > clock framework could (and possibly sh
On Fri, Aug 10, 2018 at 08:40:17AM -0700, Doug Anderson wrote:
> On Fri, Aug 10, 2018 at 3:52 AM, Mark Brown wrote:
> > This is more about matching the data rate between the two drivers - the
> > clock framework could (and possibly should) reasonably return an error
> > here, we're trying to ensu
Hi,
On Fri, Aug 10, 2018 at 3:52 AM, Mark Brown wrote:
> On Thu, Aug 09, 2018 at 11:03:55AM -0700, Doug Anderson wrote:
>> On Fri, Aug 3, 2018 at 5:18 AM, wrote:
>
>> > Also, spi core framework will set the transfer speed to controller max
>> > frequency
>> > if transfer frequency is greater th
On Thu, Aug 09, 2018 at 11:03:55AM -0700, Doug Anderson wrote:
> On Fri, Aug 3, 2018 at 5:18 AM, wrote:
> > Also, spi core framework will set the transfer speed to controller max
> > frequency
> > if transfer frequency is greater than controller max frequency.
> > Please mention if you have a ot
Hi,
On Thu, Aug 9, 2018 at 11:24 AM, Trent Piepho wrote:
> On Thu, 2018-08-09 at 11:03 -0700, Doug Anderson wrote:
>> On Fri, Aug 3, 2018 at 5:18 AM, wrote:
>> > > > + if (of_property_read_u32(pdev->dev.of_node,
>> > > > "spi-max-frequency",
>> > > > + &spi-
On Thu, 2018-08-09 at 11:03 -0700, Doug Anderson wrote:
> On Fri, Aug 3, 2018 at 5:18 AM, wrote:
> > > > + if (of_property_read_u32(pdev->dev.of_node, "spi-max-frequency",
> > > > + &spi->max_speed_hz)) {
> >
> >
> > > Why does this need to come from DT?
> >
Hi,
On Fri, Aug 3, 2018 at 5:18 AM, wrote:
>>> + if (of_property_read_u32(pdev->dev.of_node, "spi-max-frequency",
>>> + &spi->max_speed_hz)) {
>
>
>> Why does this need to come from DT?
>
>
> This is required to set the SPI controller max frequency.
> As it is
Hi Stephen and Mark,
Do you mean spi-rx-delay-us and spi-tx-delay-us properties? Those are
documented but don't seem to be used. There's also the delay_usecs
part
of the spi_transfer structure, which may be what you're talking
about.
delay_usecs is for inter-transfer delays within a message
On Thu, May 03, 2018 at 03:34:43PM -0600, Girish Mahadevan wrote:
> This driver supports GENI based SPI Controller in the Qualcomm SOCs. The
> Qualcomm Generic Interface (GENI) is a programmable module supporting a
> wide range of serial interfaces including SPI. This driver supports SPI
> operatio
On Thu, May 24, 2018 at 10:25:58AM -0600, Mahadevan, Girish wrote:
> The reason I have the cur_speed_hz is that there is a max_speed_hz which
> is the max frequency the slave can do; but every transfer can also
> specify a speed_hz and override this.
Every transfer *will* specify a speed, you sho
Hi Mark, Stephen
On 5/22/2018 11:30 AM, Mark Brown wrote:
>> That's good. The problem I see is that we have to specify the max
>> frequency in the controller/bus node, and also in the child/slave node.
>> It should only need to be specified in the slave node, so making the
>> cur_speed_hz equal th
On Mon, May 21, 2018 at 03:45:09PM -0600, Mahadevan, Girish wrote:
> I can resubmit the SPI binding documentation as part of this patch series.
Yes, and realy I'd expect to see the SPI subdevices being documented in
a separate SPI binding document rather than just lumped in with the
parent docume
On Tue, May 22, 2018 at 09:46:39AM -0700, Stephen Boyd wrote:
> Quoting Mahadevan, Girish (2018-05-21 08:52:47)
> > Not sure I follow, the intention is to run the controller clock based on
> > the slave's max frequency.
> That's good. The problem I see is that we have to specify the max
> frequen
Quoting Mahadevan, Girish (2018-05-21 08:52:47)
> Hi Stephen
>
> On 5/11/2018 4:30 PM, Stephen Boyd wrote:
>
> >> + if (mode & SPI_CPHA)
> >> + cpha |= CPHA;
> >> +
> >> + if (spi_slv->mode & SPI_CS_HIGH)
> >> + demux_output_inv |= BIT(spi_slv->chip_select)
Hi Mark,
On 5/17/2018 1:21 AM, Mark Brown wrote:
> On Mon, May 07, 2018 at 02:29:45PM -0600, Mahadevan, Girish wrote:
>> On 5/3/2018 5:38 PM, Mark Brown wrote:
>
>>> This is a DT based driver but there is no binding documentation.
>>> Binding documentation is required for any new DT stuff.
>
>>
Hi Stephen
On 5/11/2018 4:30 PM, Stephen Boyd wrote:
>> + if (mode & SPI_CPHA)
>> + cpha |= CPHA;
>> +
>> + if (spi_slv->mode & SPI_CS_HIGH)
>> + demux_output_inv |= BIT(spi_slv->chip_select);
>> +
>> + if (spi_slv->controller_data) {
>> +
On Mon, May 07, 2018 at 02:29:45PM -0600, Mahadevan, Girish wrote:
> On 5/3/2018 5:38 PM, Mark Brown wrote:
> > This is a DT based driver but there is no binding documentation.
> > Binding documentation is required for any new DT stuff.
> The DT documentation for the SPI driver was done as part o
Quoting Girish Mahadevan (2018-05-03 14:34:43)
> diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
> index 9b31351..358d60a 100644
> --- a/drivers/spi/Kconfig
> +++ b/drivers/spi/Kconfig
> @@ -564,6 +564,18 @@ config SPI_QUP
> This driver can also be built as a module. If so, the mo
Hi Mark
On 5/3/2018 5:38 PM, Mark Brown wrote:
> On Thu, May 03, 2018 at 03:34:43PM -0600, Girish Mahadevan wrote:
>> This driver supports GENI based SPI Controller in the Qualcomm SOCs. The
>> Qualcomm Generic Interface (GENI) is a programmable module supporting a
>> wide range of serial interfac
On Thu, May 03, 2018 at 03:34:43PM -0600, Girish Mahadevan wrote:
> This driver supports GENI based SPI Controller in the Qualcomm SOCs. The
> Qualcomm Generic Interface (GENI) is a programmable module supporting a
> wide range of serial interfaces including SPI. This driver supports SPI
> operatio
This driver supports GENI based SPI Controller in the Qualcomm SOCs. The
Qualcomm Generic Interface (GENI) is a programmable module supporting a
wide range of serial interfaces including SPI. This driver supports SPI
operations using FIFO mode of transfer.
Signed-off-by: Girish Mahadevan
---
dri
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