On Mon, Apr 29, 2019 at 01:11:43PM -0700, Palmer Dabbelt wrote:
> On Mon, 22 Apr 2019 08:44:30 PDT (-0700), guo...@kernel.org wrote:
> >From: Guo Ren
> >
> >The current riscv linux implementation requires SOC system to support
> >memory coherence between all I/O devices and CPUs. But some SOC syst
On Mon, 22 Apr 2019 08:44:30 PDT (-0700), guo...@kernel.org wrote:
From: Guo Ren
The current riscv linux implementation requires SOC system to support
memory coherence between all I/O devices and CPUs. But some SOC systems
cannot maintain the coherence and they need support cache clean/invalid
On 4/26/19 11:42 AM, Arnd Bergmann wrote:
EXTERNAL MAIL
On Fri, Apr 26, 2019 at 6:06 PM Guo Ren wrote:
On Thu, Apr 25, 2019 at 11:50:11AM +0200, Arnd Bergmann wrote:
On Wed, Apr 24, 2019 at 4:23 PM Christoph Hellwig wrote:
You could probably get away with allowing uncached mappings only
On Fri, Apr 26, 2019 at 6:06 PM Guo Ren wrote:
> On Thu, Apr 25, 2019 at 11:50:11AM +0200, Arnd Bergmann wrote:
> > On Wed, Apr 24, 2019 at 4:23 PM Christoph Hellwig wrote:
> >
> > You could probably get away with allowing uncached mappings only
> > for huge pages, and using one or two of the bit
Hi Arnd,
On Thu, Apr 25, 2019 at 11:50:11AM +0200, Arnd Bergmann wrote:
> On Wed, Apr 24, 2019 at 4:23 PM Christoph Hellwig wrote:
> >
> > On Wed, Apr 24, 2019 at 12:45:56PM +, Gary Guo wrote:
> > > The RISC-V privileged spec is explicitly designed to allow the
> > > techniques described abov
On Wed, Apr 24, 2019 at 4:23 PM Christoph Hellwig wrote:
>
> On Wed, Apr 24, 2019 at 12:45:56PM +, Gary Guo wrote:
> > The RISC-V privileged spec is explicitly designed to allow the
> > techniques described above (this is the sole purpose of MSTATUS.TVM). It
> > might be as high performance as
On Wed, Apr 24, 2019 at 12:45:56PM +, Gary Guo wrote:
> The RISC-V privileged spec is explicitly designed to allow the
> techniques described above (this is the sole purpose of MSTATUS.TVM). It
> might be as high performance as a hardware with H-extension, but is
> definitely a legit use cas
On 24/04/2019 06:57, Guo Ren wrote:
> Hi Gary,
>
> On Wed, Apr 24, 2019 at 03:21:14AM +, Gary Guo wrote:
>>> Look:
>>> linux-next git:(riscv_asid_allocator_v2)$ grep GLOBAL arch/riscv -r
>>> arch/riscv/include/asm/pgtable-bits.h:#define _PAGE_GLOBAL(1 << 5)/*
>>> Global */
>>> arch/r
Hi Gary,
On Wed, Apr 24, 2019 at 03:21:14AM +, Gary Guo wrote:
> > Look:
> > linux-next git:(riscv_asid_allocator_v2)$ grep GLOBAL arch/riscv -r
> > arch/riscv/include/asm/pgtable-bits.h:#define _PAGE_GLOBAL(1 << 5)/*
> > Global */
> > arch/riscv/include/asm/pgtable-bits.h:
nel.org; Mike
> Rapoport ; Vincent Chen ;
> Greentime Hu ; ren_...@c-sky.com; linux-
> ri...@lists.infradead.org; Marek Szyprowski ;
> Robin Murphy ; Scott Wood ;
> tech-privile...@lists.riscv.org
> Subject: Re: [PATCH] riscv: Support non-coherency memory model
>
> Hi Gary,
>
&
Hi Gary,
On Tue, Apr 23, 2019 at 03:57:30PM +, Gary Guo wrote:
> >>> Another point is we could get more attribute bits by modify the riscv
> >>> spec:
> >>> - Remove Global bit, I think it's duplicate with the User bit in linux.
> >>
> >> It is in Linux, but it is conceptually very different
On 23/04/2019 16:46, Guo Ren wrote:
> On Tue, Apr 23, 2019 at 07:55:48AM +0200, Christoph Hellwig wrote:
>> On Tue, Apr 23, 2019 at 08:13:48AM +0800, Guo Ren wrote:
We should probably start a working group for this ASAP unless we can
get another working group to help taking care of it.
On Tue, Apr 23, 2019 at 07:55:48AM +0200, Christoph Hellwig wrote:
> On Tue, Apr 23, 2019 at 08:13:48AM +0800, Guo Ren wrote:
> > > We should probably start a working group for this ASAP unless we can
> > > get another working group to help taking care of it.
> > Good news, I prefer to use instruct
On Tue, Apr 23, 2019 at 08:13:48AM +0800, Guo Ren wrote:
> > We should probably start a working group for this ASAP unless we can
> > get another working group to help taking care of it.
> Good news, I prefer to use instructions directly instead of SBI_CALL.
>
> Our instruction is "dcache.c/iva %0
Hi,
I love your patch! Yet something to improve:
[auto build test ERROR on linus/master]
[also build test ERROR on v5.1-rc6 next-20190418]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
https://github.com/0day-ci/linux/commits/guoren-
Thx Christoph,
On Mon, Apr 22, 2019 at 06:18:14PM +0200, Christoph Hellwig wrote:
> On Mon, Apr 22, 2019 at 11:44:30PM +0800, guo...@kernel.org wrote:
> > - Add _PAGE_COHERENCY bit in current page table entry attributes. The bit
> >designates a coherence for this page mapping. Software set th
On Mon, Apr 22, 2019 at 11:44:30PM +0800, guo...@kernel.org wrote:
> - Add _PAGE_COHERENCY bit in current page table entry attributes. The bit
>designates a coherence for this page mapping. Software set the bit to
>tell the hardware that the region of the page's memory area must be
>co
From: Guo Ren
The current riscv linux implementation requires SOC system to support
memory coherence between all I/O devices and CPUs. But some SOC systems
cannot maintain the coherence and they need support cache clean/invalid
operations to synchronize data.
Current implementation is no problem
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