On 2016/11/25 11:45, Jiancheng Xue wrote:
>
> On 2016/11/21 10:58, Jiancheng Xue wrote:
>> Hi Philipp,
>>
>>> On 2016/11/15 18:43, Philipp Zabel wrote:
Hi Jiancheng,
Am Dienstag, den 15.11.2016, 15:09 +0800 schrieb Jiancheng Xue:
> Add a polarity cell for reset line specifier.
On 2016/11/21 10:58, Jiancheng Xue wrote:
> Hi Philipp,
>
>> On 2016/11/15 18:43, Philipp Zabel wrote:
>>> Hi Jiancheng,
>>>
>>> Am Dienstag, den 15.11.2016, 15:09 +0800 schrieb Jiancheng Xue:
Add a polarity cell for reset line specifier. If the reset line
is asserted when the register
Hi Philipp,
On 2016/11/16 11:17, Jiancheng Xue wrote:
> Hi Philipp,
>
> On 2016/11/15 18:43, Philipp Zabel wrote:
>> Hi Jiancheng,
>>
>> Am Dienstag, den 15.11.2016, 15:09 +0800 schrieb Jiancheng Xue:
>>> Add a polarity cell for reset line specifier. If the reset line
>>> is asserted when the reg
Hi Philipp,
On 2016/11/15 18:43, Philipp Zabel wrote:
> Hi Jiancheng,
>
> Am Dienstag, den 15.11.2016, 15:09 +0800 schrieb Jiancheng Xue:
>> Add a polarity cell for reset line specifier. If the reset line
>> is asserted when the register bit is 1, the polarity is
>> normal. Otherwise, it is inver
Hi Jiancheng,
Am Dienstag, den 15.11.2016, 15:09 +0800 schrieb Jiancheng Xue:
> Add a polarity cell for reset line specifier. If the reset line
> is asserted when the register bit is 1, the polarity is
> normal. Otherwise, it is inverted.
>
> Signed-off-by: Jiancheng Xue
> ---
> .../devicetree/b
Add a polarity cell for reset line specifier. If the reset line
is asserted when the register bit is 1, the polarity is
normal. Otherwise, it is inverted.
Signed-off-by: Jiancheng Xue
---
.../devicetree/bindings/clock/hisi-crg.txt | 11 ---
arch/arm/boot/dts/hi3519.dtsi
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