On Fri, Apr 5, 2019 at 8:52 PM Evan Green wrote:
> On Fri, Apr 5, 2019 at 12:28 AM Rajneesh Bhardwaj
> wrote:
> > On Mon, Apr 01, 2019 at 11:05:04AM -0700, Evan Green wrote:
> > This register is a 32 bit register untill ICL generation and a recent patch
> > from Rajat fixed the overflow https://
On Fri, Apr 5, 2019 at 12:28 AM Rajneesh Bhardwaj
wrote:
>
> On Mon, Apr 01, 2019 at 11:05:04AM -0700, Evan Green wrote:
> > The PMC driver performs a 32-bit read on the sleep s0 residency counter,
> > followed by a hard-coded multiplication to convert into microseconds.
> > The maximum value this
On Mon, Apr 01, 2019 at 11:05:04AM -0700, Evan Green wrote:
> The PMC driver performs a 32-bit read on the sleep s0 residency counter,
> followed by a hard-coded multiplication to convert into microseconds.
> The maximum value this counter could have would be 0x*0x64
> microseconds, which b
The PMC driver performs a 32-bit read on the sleep s0 residency counter,
followed by a hard-coded multiplication to convert into microseconds.
The maximum value this counter could have would be 0x*0x64
microseconds, which by my calculations is about 4.9 days. This is well
within a reasonabl
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