RE: [PATCH] perf/x86/intel: Update ICL Core and Package C-state event counters

Thank you Peter for pointing out my miss, I appreciate that sincerely. > * MSR_CORE_C3_RESIDENCY: CORE C3 Residency Counter > * perf code: 0x01 > * Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL,GLM, > -

Re: [PATCH] perf/x86/intel: Update ICL Core and Package C-state event counters

On Fri, Jul 26, 2019 at 05:08:46PM +0800, Harry Pan wrote: > Ice Lake microarchitecture inherits Cannon Lake, it has CC1/PC8/PC9/PC10 > residency counters. > > Update the list of Ice Lake PMU event counters from the snb_cstates[] list > of events to the cnl_cstates[] list of events, which keeps al

[PATCH] perf/x86/intel: Update ICL Core and Package C-state event counters

Ice Lake microarchitecture inherits Cannon Lake, it has CC1/PC8/PC9/PC10 residency counters. Update the list of Ice Lake PMU event counters from the snb_cstates[] list of events to the cnl_cstates[] list of events, which keeps all previously supported events and also adds the CORE_C1, PKG_C8, PKG_