On Fri, 11 Dec 2020 at 15:17, Marcin Wojtas wrote:
>
> From: Alex Leibovich
>
> Automatic Clock Gating is a feature used for the power
> consumption optimisation. It turned out that
> during early init phase it may prevent the stable voltage
> switch to 1.8V - due to that on some platfroms an end
wt., 15 gru 2020 o 09:04 Adrian Hunter napisaĆ(a):
>
> On 11/12/20 4:16 pm, Marcin Wojtas wrote:
> > From: Alex Leibovich
> >
> > Automatic Clock Gating is a feature used for the power
> > consumption optimisation. It turned out that
> > during early init phase it may prevent the stable voltage
>
On 11/12/20 4:16 pm, Marcin Wojtas wrote:
> From: Alex Leibovich
>
> Automatic Clock Gating is a feature used for the power
> consumption optimisation. It turned out that
> during early init phase it may prevent the stable voltage
> switch to 1.8V - due to that on some platfroms an endless
platf
From: Alex Leibovich
Automatic Clock Gating is a feature used for the power
consumption optimisation. It turned out that
during early init phase it may prevent the stable voltage
switch to 1.8V - due to that on some platfroms an endless
printout in dmesg can be observed:
"mmc1: 1.8V regulator out
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